Optimized gate implants for reducing dopant effects during gate etching

A method of fabricating an integrated circuit on a laminate comprising a gate dielectric layer between a gate electrode layer and a substrate, said method comprising the steps of:

• a) aligning within an alignment tolerance a first implant mask over said gate electrode layer, said first implant mask to allow implantation of a first dopant material into said gate electrode layer at a location at which a first gate of said integrated circuit is to be formed, said first implant mask sized so that said first dopant material does not extend beyond an edge of said first gate plus said alignment tolerance;
• b) implanting said first dopant material into said gate electrode layer such that said first dopant material does not extend beyond said edge of said first gate plus said alignment tolerance;
• c) applying a gate mask over said first dopant material;
• and
• d) removing said gate electrode layer not under said gate mask using an etchant, said etchant inducing a detectable endpoint signal upon reaching said gate dielectric layer.

A laminate for fabricating an integrated circuit, said laminate comprising:

• a substrate layer;
• a gate dielectric layer adjacent to said substrate layer;
• and
• a gate electrode layer adjacent to said gate dielectric layer, said gate electrode layer comprising:
• a first portion doped with a first dopant material, said first portion substantially corresponding to a location at which a first gate of said integrated circuit is to be formed;
• and
• a second portion doped with a second dopant material, wherein more of said gate electrode layer is doped with said second dopant material than with said first dopant material and wherein said gate electrode layer doped with said second dopant material is etched away at a faster rate than said gate electrode layer doped with said first dopant material.