Method for controlling and monitoring a chemical mechanical polishing process
AssigneeMacronix International Co., Ltd.
InventorsChun-Lien Su, Chi-Yuan Chin, Shih-Keng Cho, Ming-Shang Chen, Yih-Shi Lin
Life of this patent
Estimating the term…
Abstract
The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.
Claims15
A method of controlling and monitoring the thickness variation of a film structure of a semiconductor wafer, said semiconductor wafer including at least one device region and a testing region, said device region and said testing region having the same film structure, said testing region is utilized, in a CMP process, to control and monitor the thickness variation of said film structure of said device region, said method comprising:
- calculating a first pattern density of said film structure of said device region;
- etching said film structure of said testing region that a second pattern density of said film structure of said testing region being substantially compatible with said first pattern density of said device region;
- and
- polishing said semiconductor wafer and monitoring the thickness variation of said film structure of said testing region.
A planarization method of a semiconductor wafer, with a plurality of shallow trenches, said semiconductor having at least one device region and a testing region, said device region having said shallow trenches and said testing region having a planar surface, said device region and said testing region having a film structure, said film structure at least having a first dielectric layer and a second dielectric layer on said first dielectric layer, said testing region is utilized, in a CMP process, to control and monitor the thickness variation of said film structure of said device region, said method comprising:
- removing a portion of said second dielectric layer on said device region and forming a plurality of the second dielectric blocks;
- calculating a first pattern density of said film structure of said device region;
- etching said film structure of said testing region that a second pattern density of said film structure of said testing region being substantially compatible with said first pattern density of said device region;
- and
- polishing said semiconductor wafer and monitoring the thickness variation of said film structure of said testing region.
Dependencies are inferred from the claim text.