US 2003/0143849 A1Published application

Method for avoiding defects produced in the CMP process

AssigneeProMOS Technologies Inc.

InventorsMing-Cheng Yang, Jiun-Fang Wang

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Abstract

A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.

Claims7

Dependent claims

A method for avoiding defects produced in the CMP process, comprising the steps of:

(a) providing a semiconductor substrate which has a plurality of predetermined contact window areas;
(b) sequentially depositing a first dielectric layer and a second dielectric layer on the semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer;
(c) performing dry etching process to form a plurality of first holes on the plurality of the predetermined contact window areas respectively, wherein each of the first holes passes through the second dielectric layer and the first dielectric layer to a predetermined depth;
(d) performing wet etching process to etch the first dielectric layer in each of the first holes to a predetermined width, and thereby a plurality of second holes are formed on the plurality of the predetermined contact window areas respectively;
(e) forming a conductive layer to fill each of the second holes;
and
(f) performing the CMP process to make the top of the conductive layer equal to the top of and the second dielectric layer, in which each top of the second holes is kept at the same level.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/393,975Filed 24 Mar 2003
Priority: TW 9010090116 Jan 2001
Published: 31 Jul 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10P 52/403
Chemomechanical polishing [CMP]: of conductive or resistive materials
H10W 20/062
Of conductive parts of the interconnections: by smoothing of conductive parts, e.g. by planarisation
H10W 20/074
Of dielectric parts thereof: of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or…
H10P
Generic processes or apparatus for the manufacture or treatment of devices covered

Family

Application09/836,219Continuation in part · filed 18 Apr 2001
Application10/393,975Continuation in part · filed 24 Mar 2003
US 2002/0155716 A1Published application
US 6,632,742 B2Related patent
US 2003/0143849 A1This patent

From the US filing history. Foreign family members aren’t listed.