Novel method of fabricating metallic local interconnections that also improves transistor performance

A method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity comprising the steps of:

• providing a semiconductor substrate;
• forming field oxide isolation regions surrounding and electrically isolating device areas and coplanar with surface of said substrate;
• forming a gate oxide on said device areas;
• depositing a conductively doped polysilicon layer on said substrate;
• depositing a silicon nitride first insulating layer on said polysilicon layer;
• patterning said first insulating layer and said polysilicon layer using a photoresist mask and anisotropic plasma etching leaving portions over said device areas to form said gate electrodes and portions of said patterned polysilicon over said field oxide isolation regions for local interconnections;
• forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation;
• depositing a conformal silicon oxide second insulating layer over said gate electrodes and elsewhere on said substrate;
• anisotropically etching back said second insulating layer thereby forming sidewall spacers on sidewalls of said gate electrodes;
• forming source/drain contact areas by ion implantation;
• depositing a silicon oxide third insulating layer on said substrate;
• polishing back said third insulating layer to said first insulating layer to form a planar surface;
• selectively removing portions of said silicon nitride first insulating layer over said patterned polysilicon layer while leaving essentially unetched said second and said third insulating layers and forming recesses in said third insulating layer over said patterned polysilicon layer;
• using a photoresist mask and anisotropic etching to etch contact openings in said third insulating layer to said substrate;
• depositing a blanket metal layer and filling said contact openings and said recesses in said third insulating layer over said patterned polysilicon layer;
• patterning said metal layer leaving portions over said contact openings and over and contacting portions of said patterned polysilicon layer to complete said local metal interconnections while leaving said metal in said recesses to improve the electrical conductivity of said patterned polysilicon layer.

A method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity comprising the steps of:

• providing a semiconductor substrate;
• forming field oxide isolation regions surrounding and electrically isolating device areas and coplanar with surface of said substrate;
• forming a gate oxide on said device areas;
• depositing a conductively doped polysilicon layer on said substrate;
• depositing a first insulating layer on said polysilicon layer;
• patterning said first insulating layer and said polysilicon layer using a-photoresist mask and anisotropic plasma etching leaving portions over said device areas to form said gate electrodes and portions of said patterned polysilicon over said field oxide isolation regions for local interconnections;
• forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation;
• depositing a conformal second insulating layer over said gate electrodes and elsewhere on said substrate;
• anisotropically etching back said second insulating layer thereby forming sidewall spacers on sidewalls of said gate electrodes;
• forming source/drain contact areas by ion implantation;
• depositing a third insulating layer on said substrate;
• polishing back said third insulating layer to said first insulating layer to form a planar surface;
• using a photoresist mask to selectively remove portions of said first insulating layer over said patterned polysilicon layer while leaving essentially unetched said second and said third insulating layers and forming recesses in said third insulating layer over said patterned polysilicon layer;
• using a photoresist mask and anisotropic etching to etch contact openings in said third insulating layer to said substrate;
• depositing a blanket metal layer and filling said contact openings and said recesses in said third insulating layer over said patterned polysilicon layer;
• patterning said metal layer leaving portions over said contact openings and over and contacting portions of said patterned polysilicon layer to complete said local metal interconnections while leaving said metal in said recesses to improve the electrical conductivity of said patterned polysilicon layer, and further portions of said patterned metal layer extending over remaining said silicon nitride layer to form crossovers for said local interconnections.

A local metal interconnect structure with low contact resistance and FET gate electrodes with improved electrical conductivity comprised of:

• a semiconductor substrate;
• field oxide isolation regions surrounding and electrically isolating device areas and coplanar with surface of said substrate;
• a gate oxide on said device areas;
• a patterned conductively doped polysilicon layer on said substrate for said FET gate electrodes and portions of said local interconnections, wherein said FET gate electrodes have lightly doped source/drain areas adjacent to said gate electrodes and source/drain contact areas;
• an insulating layer having a planar surface on said patterned polysilicon layer and said insulating layer having self-aligned recesses over said patterned polysilicon layer, and said insulating layer having contact openings to said substrate;
• a patterned metal layer having portions over and in said contact openings and over and in said recesses to improve the electrical conductivity of said patterned polysilicon layer, and said patterned metal layer also extending over said insulating layer to complete said local metal interconnections.