Method for radiation hardening N-channel MOS transistors

Abstract

An N-channel radiation-hardened transistor has source and drain regions that are fully enclosed by an intrinsically radiation-hardened thin gate-oxide. which substantially reduces radiation-induced intra-device and inter-device leakage currents. The width of the polysilicon gate directly between the source and drain can be the minimum feature size allowed by the design rules of a given process. The width of the polysilicon surrounding the device is chosen by design rules from the minimum allowed to some wider value to allows the polysilicon overlap to be sufficient to self-align the source and drain without compromising the doping under the field region. The polysilicon should be sufficiently wide so that it completely overlaps any transitional oxide such as LOCOS or trench oxide. The gate capacitance of the N-channel transistor can be tuned to balance SEU hardness and switching performance. An alternative radiation-hardened transistor for high-current applications includes an annular transistor design in which the transistor is completely surrounded with a thin gate oxide to substantially reduce radiation-induced inter-device leakage currents.

Dependencies are inferred from the claim text.