Method for achieving high self-aligning vertical gate studs relative to the support isolation level

A vertical gate transistor comprising:

• a trench formed within a semiconductor substrate;
• a gate oxide formed on the sidewall of the trench;
• a gate conductor formed within the trench;
• a vertical gate stud protruding above the surface of the semiconductor substrate and comprising
• a conductive first region contacting the gate conductor formed within the trench and extending a first distance above the semiconductor substrate;
• a conductive second region contacting the first region and extending above the first region, the conductive second region and first conductive region having differing etch resistance characteristics;
• and
• a gate contact formed above and contacting said second conductive region.

A method of forming a vertical gate semiconductor device comprising:

• forming a patterned layer on a top surface of a semiconductor wafer, the patterned layer having openings therein defining a trench region;
• forming a trench in the trench region;
• filling the trench with a gate conductor to a level substantially coplanar with the pad layer;
• etching back the gate conductor to a level below the top surface of the semiconductor wafer;
• applying a conformal layer of first gate stud material atop the pad layer and within the deep trench;
• planarizing the conformal layer of first gate stud material to a level substantially coplanar with the pad layer;
• forming a layer of second gate stud material in a recess formed within the conformal layer of first gate stud material, the second gate stud material protruding above the level of the pad layer;
• etching back the conformal layer of first gate stud material with an etchant that does not substantially etch back the second gate stud material;
• forming a first insulator layer over the remaining conformal layer of first gate stud material and the second gate stud material;
• forming a second insulator layer over the first insulator layer;
• and
• removing the first and second insulator layer from a region on the second gate stud material to form a gate contact.

A memory cell comprising:

• a trench formed within a top surface of a semiconductor substrate;
• a capacitor formed within a lower portion of the trench, comprising a buried layer adjacent the trench, an insulator layer formed on a sidewall of the trench, and a conductor formed within the lower portion of the trench;
• a conductive buried strap region electrically coupled to the capacitor;
• a gate oxide formed on a sidewall of an upper portion of the trench;
• a gate conductor formed within the upper portion of the trench;
• and
• a gate stud extending above the top surface of the semiconductor substrate and comprising:
• a first material formed on the gate conductor, the first material be subject to etching by a pre-selected etchant,
• a second material formed on the first material and be resistant to etching by the pre-selected etchant,
• wherein the first material and the second material provide an conductive element that extends the gate conductor to a level of a metal layer above the memory cell.