Method for manufacturing horizontal surrounding gate flash memory cell

A structure of a horizontal surrounding gate (HSG) flash memory cell, comprising:

• a substrate, wherein the substrate comprises:
• an isolation region;
• a channel region, wherein the size of the isolation region is larger than the size of the channel region, and the channel region is all covered by the isolation region;
• a trench located on the isolation region;
• and
• a source and a drain, wherein the source and the drain are located beside two sides of the channel region respectively;
• a plurality of spacers located beside a sidewall of the trench;
• a crystallized semiconductor film located on a portion of the trench, wherein the crystallized semiconductor film is connected with the source and the drain respectively;
• an oxide layer;
• a floating gate;
• a dielectric layer;
• and
• a control gate, wherein the crystallized semiconductor film is surrounded and encompassed by the oxide layer, a portion of the floating gate, a portion of the dielectric layer, and the control gate in turn, and the trench and the spacers are covered by an other portion of the floating gate, an other portion of the dielectric layer, and the control gate in sequence.

A method for manufacturing a horizontal surrounding gate (HSG) flash memory cell, comprising:

• providing a substrate comprising a isolation region and a channel region formed thereon, wherein the size of the isolation region is larger than the size of the channel region, and the channel region is all covered by the isolation region, and the isolation region is filled with an insulating material;
• removing a portion of the insulating material in the isolation region to form a trench on the isolation region in the substrate;
• forming a plurality of spacers in the trench and beside a sidewall of the trench;
• forming a sacrificial layer to cover the isolation region, the trench, and the spacers, and the trench is filled up with the sacrificial layer;
• forming an amorphous semiconductor film to cover the substrate, the spacers, and the sacrificial layer;
• performing a re-crystallization step to make the amorphous semiconductor film covering the substrate integrate into the substrate, and to make the amorphous semiconductor film located on the isolation region change into a crystallized semiconductor film;
• removing a portion of the crystallized semiconductor film to leave an other portion of the crystallized semiconductor film located on the channel region, and to expose a portion of the spacers and a portion of the sacrificial layer;
• removing the sacrificial layer to expose a bottom of the trench, so as to form a hollow region constituted by the other portion of the crystallized semiconductor film, the spacers, and the bottom of the trench, and to form a plurality of slots between the other portion of the crystallized semiconductor film and the trench;
• forming an oxide layer to cover the other portion of the crystallized semiconductor film;
• forming a floating gate to cover the oxide layer, a sidewall of the hollow region, and a bottom of the hollow region;
• forming a dielectric layer to cover the floating gate;
• and
• forming a control gate to cover the dielectric layer.