Method of preventing high Icc at start-up in zero-power EEPROM cells for PLD applications

A method for manufacturing a CMOS memory cell including:

• a PMOS transistor having a source coupled to Vcc, a drain and a floating gate;
• an NMOS transistor with a source coupled to Vss, a drain in common with the PMOS transistor and a floating gate in common with the PMOS transistor;
• a control capacitor having one terminal in common with the floating gate;
• and a tunneling capacitor having one terminal in common with the floating gate and a second terminal;
• and a pass transistor having a source-drain path connected to the second terminal of the tunneling capacitor, the method comprising the steps of:
• forming the NMOS transistor with a first threshold value;
• forming the PMOS transistor with a second threshold value;
• and
• altering the second threshold value, so that charge cannot be provided on the floating gate causing both the NMOS transistor and the PMOS transistor to be turned on together.

A method for manufacturing a CMOS memory cell including:

• a PMOS transistor having a source coupled to Vcc, a drain and a floating gate;
• an NMOS transistor with a source coupled to Vss, a drain in common with the PMOS transistor and a floating gate in common with the PMOS transistor;
• a control capacitor having one terminal in common with the floating gate;
• and a tunneling capacitor having one terminal in common with the floating gate and a second terminal;
• and a pass transistor having a source-drain path connected to the second terminal of the tunneling capacitor, the method comprising the steps of:
• forming the NMOS transistor with a first threshold value;
• forming the PMOS transistor with a second threshold value;
• and
• altering the first threshold value and the second threshold value so that charge cannot be provided to the floating gate causing both the NMOS transistor and the PMOS transistor to be turned on together.

An array of CMOS memory cells, each memory cell in the comprising:

• a PMOS transistor having a source coupled to Vcc, a drain and a floating gate, the PMOS transistor having ion implantation in a substrate between its source and drain to set a first threshold value for the PMOS transistor;
• an NMOS transistor with a source coupled to Vss, a drain in common with the PMOS transistor and a floating gate in common with the PMOS transistor;
• a control capacitor having one terminal in common with the floating gate;
• a tunneling capacitor having one terminal in common with the floating gate and a second terminal;
• and a pass transistor having a source-drain path connected to the second terminal of the tunneling capacitor,
• wherein the first threshold value is set so that charge cannot be provided to the floating gate causing both the NMOS transistor and the PMOS transistor to be turned on together.

An array of CMOS memory cells, each memory cell in the comprising:

• a PMOS transistor having a source coupled to Vcc, a drain and a floating gate;
• an NMOS transistor with a source coupled to Vss, a drain in common with the PMOS transistor and a floating gate in common with the PMOS transistor, the NMOS transistor having ion implantation in a substrate between its source and drain to set a first threshold value for the NMOS transistor;
• a control capacitor having one terminal in common with the floating gate;
• a tunneling capacitor having one terminal in common with the floating gate and a second terminal;
• and a pass transistor having a source-drain path connected to the second terminal of the tunneling capacitor,
• wherein the first threshold value is set so that charge cannot be provided to the floating gate causing both the NMOS transistor and the PMOS transistor to be turned on together.

An array of CMOS memory cells, each memory cell in the comprising:

• a PMOS transistor having a source coupled to Vcc, a drain and a floating gate, the PMOS transistor having ion implantation in a substrate between its source and drain to set a first threshold value for the PMOS transistor;
• an NMOS transistor with a source coupled to Vss, a drain in common with the PMOS transistor and a floating gate in common with the PMOS transistor, the NMOS transistor having ion implantation in a substrate between its source and drain to set a second threshold value for the NMOS transistor;
• a control capacitor having one terminal in common with the floating gate;
• a tunneling capacitor having one terminal in common with the floating gate and a second terminal;
• and a pass transistor having a source-drain path connected to the second terminal of the tunneling capacitor,
• wherein the first threshold value and the second threshold value are set so that charge cannot be provided to the floating gate causing both the NMOS transistor and the PMOS transistor to be turned on together.