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US 2003/0142564 A1Published application
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Wendell P. Noble
Life of this patent
Estimating the term…
Abstract
A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second source/drain regions and a body region. The transistor also includes a gate that is formed along a side of the pillar. A trench capacitor is also included in the cell. A first plate of the trench capacitor is formed integral with the first source/drain region. A second plate is disposed adjacent to the first plate and separated from the first plate by a gate oxide.
Claims28
A memory cell, comprising:
- an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
- wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;
- a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
- and
- a second plate of the trench capacitor.
2 more elements
A memory device, comprising:
- an array of memory cells, wherein at least one cell includes:
- an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor includes a first source/drain region, and a body region;
- wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion of the pillar also functions as a first plate of a trench capacitor;
- a second plate of the trench capacitor;
- a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to form columns of memory cells;
- a number of word lines, each word line disposed orthogonally to the bit lines with a single word line in each of a number of trenches between rows of the memory cells;
- and
- wherein each single word line addresses gates of access transistors on a first side of a trench, and is isolated from access transistors on a second side of the trench.
5 more elements
A memory array comprising:
- an array of memory cells, each memory cell including
- an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
- wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion the pillar also functions as a first plate of a trench capacitor;
- a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
- a second plate of the trench capacitor;
- a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells.
3 more elements
A memory cell, comprising:
- an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
- wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;
- a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
- a second plate of the trench capacitor substantially surrounding the first plate portion of the lower pillar structure;
- and
- an ohmic contact that couples the second plate to a layer of semiconductor material.
3 more elements
A memory device, comprising:
- an array of memory cells, wherein at least one cell includes:
- an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
- wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion the pillar also functions as a first plate of a trench capacitor;
- a second plate of the trench capacitor substantially surrounding the first plate portion of the pillar;
- an ohmic contact that couples the second plate to a layer of semiconductor material;
- a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to form columns of memory cells;
- a number of word lines, each word line disposed orthogonally to the bit lines with a single word line in each of a number of trenches between rows of the memory cells;
- and
- wherein each single word line addresses gates of access transistors on a first side of a trench, and is isolated from access transistors on a second side of the trench.
6 more elements
A memory array comprising:
- an array of memory cells, each memory cell including
- an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
- wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion of the pillar also functions as a first plate of a trench capacitor;
- a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
- a second plate of the trench capacitor substantially surrounding the first plate portion of the pillar;
- an ohmic contact that couples the second plate to a layer of semiconductor material;
- a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells.
4 more elements
A memory cell, comprising:
- an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
- wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;
- a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
- a second polysilicon plate of the trench capacitor substantially surrounding the first plate portion of the lower pillar structure;
- and
- an ohmic contact that couples the second plate to a layer of semiconductor material.
3 more elements
Dependencies are inferred from the claim text.