Stacked fill structures for support of dielectric layers
AssigneeInternational Business Machines Corporation
InventorsTimothy G. Dunham, Howard S. Landis, William T. Motsiff
Life of this patent
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Abstract
Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.
Claims36
A semiconductor device comprising:
- a first wiring level having a first conductive fill shape embedded in a first dielectric;
- a second wiring level having a second conductive fill shape embedded in a second dielectric;
- and
- a conductive via extending between and joining said first and second conductive fill shapes.
A semiconductor device comprising:
- a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric;
- at least some of said fill shapes in at least two adjacent wiring levels being co-aligned;
- and
- where said fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level.
A semiconductor device comprising:
- a first wiring level, said first wiring level comprising a conductive wires and a multiplicity of conductive fill shapes embedded in a first dielectric material;
- a multiplicity of higher wiring levels, each higher wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a second dielectric material;
- at least some of said fill shapes in one or more pairs of adjacent wiring levels being co-aligned;
- and
- where said fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each pair of adjacent wiring levels.
A semiconductor device comprising:
- a first wiring level having a first conductive fill shape having corners, embedded in a first dielectric;
- a second wiring level having a second conductive fill shape having corners, embedded in a second dielectric, said second conductive fill shape co-aligned with said first fill shape;
- and
- a conductive via aligned with each corner of said first and second fill shapes and extending between and joining said first and second conductive fill shapes.
A semiconductor device comprising:
- a first wiring level having a first conductive fill shape having corners, embedded in a first dielectric;
- a second wiring level having a second conductive fill shape having corners, embedded in a second dielectric, said second conductive fill shape co-aligned with said first fill shape;
- and
- at least two conductive vias each aligned with a corner of said first and second fill shapes and extending between and joining said first and second conductive fill shapes.
A method of fabricating a semiconductor device, comprising:
- providing a substrate;
- forming on said substrate, a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric;
- at least some of said fill shapes in at least two adjacent wiring levels being co-aligned;
- and
- where said fill shapes on adjacent levels are aligned, forming one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level.
A method of fabricating a semiconductor device, comprising:
- providing a substrate;
- forming a first wiring level on said substrate, said first wiring level comprising a conductive wires and a multiplicity of conductive fill shapes embedded in a first dielectric material;
- forming a multiplicity of higher wiring levels on said first wiring level, each higher wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a second dielectric material;
- at least some of said fill shapes in one or more pairs of adjacent wiring levels being co-aligned;
- and
- where said fill shapes on adjacent levels are aligned, forming one or more conductive vias extending between and joining each co-aligned fill shape in each pair of adjacent wiring levels.
A method of designing a semiconductor device having wiring levels containing wires and fill shapes interspersed with interconnecting via levels containing vias, comprising:
- (a) selecting a pair of adjacent wiring levels;
- (b) finding pairs of vertically aligned fill shapes in said adjacent wiring levels;
- and
- (c) creating and placing, in the interconnecting via levels between said adjacent wiring levels, one or more vias to interconnect said pairs of fill shapes.
A method of designing a semiconductor device having wiring levels interspersed with interconnecting via levels, comprising:
- (a) placing fill shapes at least some of said wiring levels;
- (b) selecting a pair of adjacent wiring levels;
- (c) finding pairs of vertically aligned fill shapes in said adjacent wiring levels;
- and
- (d) creating and placing, in the interconnecting via levels between said adjacent wiring levels, one or more vias to interconnect said pairs of fill shapes.
Dependencies are inferred from the claim text.