Fabrication method for flash memory
AssigneeWinbond Electronics Corp.
InventorWen-Yueh Jang
Life of this patent
Estimating the term…
Abstract
The present invention describes a method for fabricating flash memory. In accordance with the present invention, the forming of the floating gate does not require an additional photolithography step. As a result, the misalignment problem between the floating gate and the active area may be resolved. On the other hand, because of the specific floating gate structure of the present invention, high coupling capacitance between the floating gate and control gate can be achieved by recessing the shallow trench isolation more. Therefore, the method does not sacrifice the whole cell size.
Claims28
A fabrication method for flash memory applied to a semiconductor substrate having an active area isolated by an isolation structure, said method comprising:
- etching said isolation structure to a depth to form a recessed isolation structure;
- forming a conformal first dielectric layer on a surface of said active area and said recessed isolation structure;
- etching said first dielectric layer to form spacers on sides of said active area edge;
- performing a thermal oxidation process to form a tunnel oxide layer on the surface of said active area;
- forming a conformal doped silicon layer over said tunnel oxide layer and said recessed isolation structure;
- filling said recessed isolation structure with a sacrificial layer;
- forming an oxide layer on and exposed surface of said doped silicon layer;
- removing said sacrificial layer and said doped silicon layer with said oxide layer serving as a mask to expose a surface of said recessed isolation structure;
- removing said oxide layer;
- forming a second dielectric layer on the surface of said doped silicon layer and said recessed isolation structure;
- forming a conductive layer over said second dielectric layer;
- patterning said conductive layer to form word lines;
- and
- performing an ion implantation using said word lines as a mask to form source/drain regions in said active area.
A flash memory structure formed on a semiconductor substrate having active area islands isolated by a recessed isolation structure, said structure comprising:
- spacers located on sides of said active area edge;
- a tunnel oxide layer formed on a surface of said active area;
- a conformal doped silicon layer formed over said tunnel oxide layer and said recessed isolation structure, wherein said conformal doped silicon layer is formed as a floating gate;
- a dielectric layer formed on a surface of said doped silicon layer and said recessed isolation structure;
- and
- a conductive layer formed over said dielectric layer, wherein said conductive layer is a control gate.
Dependencies are inferred from the claim text.