Semiconductor memory device and method for producing the same
AssigneeSony Corporation
InventorYasuyuki Ito
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device able to increase the effective area of a capacitor in a memory cell and ensure a sufficient amount of charge contained in a read signal while maintaining the smallest cell area and a method for producing the same, wherein a first node electrode, a first ferroelectric film, and plate electrodes form four ferroelectric capacitors, plate electrodes, a second ferroelectric film, and a second node electrode form other four ferroelectric capacitors, the first node electrode is electrically connected to the second node electrode, a capacitor below a plate electrode is connected in parallel with the capacitor above the plate electrode, and these two capacitors connected in parallel form a memory cell storing 1 bit of data.
Claims12
A semiconductor memory device comprising:
- a MIS transistor for selecting a memory cell;
- a common node electrode electrically connected with an impurity diffusing region of the MIS transistor;
- a bit line electrically connected with another impurity diffusing region of the MIS transistor;
- and
- a plurality of storage means connected to the common node electrode, wherein
- each said storage means includes a plurality of capacitors electrically connected with each other in parallel.
A semiconductor memory device comprising a plurality of memory cell blocks each including
- a MIS transistor for selecting a memory cell;
- a common node electrode electrically connected with an impurity diffusing region of the MIS transistor;
- a bit line electrically connected with another impurity diffusing region of the MIS transistor;
- and
- a plurality of storage means connected to the common node electrode, wherein
- each said storage means includes a plurality of capacitors electrically connected with each other in parallel, and
- said common node electrodes of different memory cell blocks are stacked so as to overlap each other.
A method for producing a semiconductor memory device comprising a MIS transistor for selecting a memory cell, N (N is a natural number, N>1) number of storage means connected with an impurity diffusing region of the MIS transistor, and a bit line electrically connected with another impurity diffusing region of the MIS transistor, wherein each said storage means includes M (M is a natural number, M>1) number of capacitors electrically connected with each other in parallel, comprising:
- a step of forming said MIS transistor on a semiconductor substrate;
- a step of forming a contact plug having a first conductivity extending to an impurity diffusing region of the MIS transistor and a contact plug having a second conductivity extending to another impurity diffusing region of the MIS transistor in an insulating film covering the semiconductor substrate formed with the MIS transistor;
- a storage means forming step for forming said N number of said storage means connected to the contact plug having the first conductivity;
- and
- a step of forming said bit line connected to the contact plug having the second conductivity.
A method for producing a semiconductor memory device comprising a plurality of memory cell blocks each including a MIS transistor for selecting a memory cell, N (N is a natural number, N>1) number of storage means connected with an impurity diffusing region of the MIS transistor, and a bit line electrically connected with another impurity diffusing region of the MIS transistor, wherein each said storage means includes M (M is a natural number, M>1) number of capacitors electrically connected with each other in parallel, and said N numbers of storage means of different memory cell blocks are stacked so as to overlap each other, comprising:
- a step of forming a plurality of said MIS transistors on a semiconductor substrate;
- a step of forming a contact plug having a first conductivity extending to an impurity diffusing region of the MIS transistor and a contact plug having a second conductivity extending to another impurity diffusing region of the MIS transistor in an insulating film covering the semiconductor substrate formed with each said MIS transistor;
- a storage means forming step for forming said N number of storage means connected to each contact plug having the first conductivity;
- and
- a step of forming said bit line connected to each contact plug having the second conductivity, wherein
- numbers of N storage means connected to different memory cell blocks are formed to overlap each other.
Dependencies are inferred from the claim text.