Idle power reduction for state machines

A state machine comprising:

• a programmable memory storing a plurality of words, each word having a plurality of bits, a word from the memory being supplied in response to an address signal, the memory being coupled to operate in response to a first clock signal;
• a selection circuit coupled to receive a last address signal representing a last word selected in the memory and connected to receive at least first and second address signals from the programmable memory, and coupled to receive signals from an external circuit, the selection circuit selecting one of the last address, the first address or the second address in response to the signals from the external circuit, the selection circuit being coupled to operate in response to a second clock signal;
• and
• a clock circuit coupled to the selection circuit for detecting when the signal selecting one of the words in the programmable memory changes, the clock circuit disabling the first clock signal when the signal selecting one of the words in the programmable memory remains unchanged from a previous state, and enabling the first clock signal when the signal selecting one of the words in the programmable memory changes to a new state

A state machine comprising:

• a programmable memory storing a plurality of words, each word having a plurality of bits, a word from the memory being supplied in response to an address signal, the memory being coupled to operate in response to a first clock signal;
• a register coupled to the memory for storing a word last provided from the memory;
• a selection circuit coupled to receive a last address signal representing a last word selected in the memory and connected to receive at least first and second address signals from the programmable memory, the selection circuit being coupled to operate in response to a second clock signal and in response to a selection signal;
• a control circuit coupled to receive signals from an external circuit, the control circuit providing the selection signal which selects one of the last address, the first address or the second address in response to the signals from the external circuit, the control circuit being coupled to operate in response to a second clock signal;
• and
• a clock circuit coupled to the control circuit to receive the selection signal and detect when the selection signal selecting one of the words in the programmable memory changes, the clock circuit disabling the first clock signal when the selection signal selecting one of the words in the programmable memory remains unchanged from a previous state, and enabling the first clock signal when the selection signal selecting one of the words in the programmable memory changes to a new state.

A state machine comprising:

• a memory storing a plurality of words representative of states of the state machine, each word having a plurality of bits, a word from the memory being supplied in response to a selection signal, the memory connected to receive a first clock signal, at least one bit in each word indicative of whether a next word to be addressed is a same word as has previously been addressed, or is a different word;
• a first plurality of external input terminals for receiving information from an external circuit;
• a control circuit having a plurality of input terminals, at least some of which are coupled to the external input terminals to receive the information therefrom, the control circuit supplying a first output signal;
• and
• a clock circuit connected to receive the first output signal and connected to receive a signal representative of the at least one bit indicative of whether a next word to be addressed is the same word or a different word, the clock circuit disabling the first clock signal when the at least one bit indicates that the same word is to be selected.