Semiconductor design/fabrication system, semiconductor design/fabrication method and semiconductor design/fabrication program

A semiconductor design/fabrication method which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising:

• selecting the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known;
• calculating a sum of said critical areas on each of the selected function blocks;
• calculating an yield based on the calculated sum of said critical areas and-defect occurrence rate information of a chip fabrication line;
• calculating information relating to fabrication cost and delivery time of the chip based on the calculated yield and fabrication management information relating to cost and fabrication period of the chip fabrication line;
• and
• selecting a combination of the function blocks constituting the chip based on the calculated information relating to the fabrication cost and the delivery time of the chip.

A semiconductor design/fabrication program to be executed by a computer, which combines a plurality of function blocks and arranges the combined function blocks on a chip, said program comprising:

• a command for selecting the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known;
• a command for calculating a sum of said critical areas on each of the selected function blocks;
• a command for calculating an yield based on the calculated sum of said critical areas and defect occurrence rate information of a chip fabrication line;
• a command for calculating information relating to fabrication cost and delivery time of the chip based on the calculated yield and fabrication management information relating to cost and fabrication period of the chip fabrication line;
• and
• a command for selecting a combination of the function blocks constituting the chip based on the calculated information relating to the fabrication cost and the delivery time of the chip.