Method of measuring the probability of failure caused only by defects, method of measuring defect limited yield, and system using the same

A method of calculating a probability of failures caused only by defects in each chip of a wafer comprising the steps of:

• determining the total number of wafer chips (m1);
• detecting defects in each said wafer chip determining the total number of chips having said defects (m2);
• determining the total number of chips which fail due to a reason other than said defects (m3);
• classifying said wafer chips having defects using probable parameters in consideration of area, size, and number of said defects;
• determining the total number of wafer chips (m4) and the total number of wafer chips which fail (m5) when said wafer chips are classified according to each said probable parameter;
• and
• calculating a probability (KR) that said wafer chips fail only due to said defects by substituting the data m1, m2, m3, m4, and m5 in the formula:
• 15 KR = 1 - 1 - KR 1 1 - KR 0 , ⁢ wherein ⁢ ⁢ KR 0 = m3 m1 - m2 ⁢ ⁢ and ⁢ ⁢ KR 1 = m5 m4 .

A method of calculating a defect limited yield (DLY) comprising:

• inspecting said blocks to detect defects in said blocks and in blocks located around said inspected blocks;
• measuring the number of said inspected blocks having failures caused by a reason other than said defects in said inspected blocks located around said inspected blocks having said defects (n1);
• measuring the number of said inspected blocks having no failures in said inspected blocks located around said inspected blocks having said defects (n2);
• measuring the number of inspected blocks having failures caused by said defects in said inspected blocks having said defects (n3);
• measuring the number of inspected blocks having no failures in said inspected blocks having said defects (n4);
• substituting data (n1) through (n4) in formula 1a
• 16 KR = 1 - 1 - KR 1 1 - KR 0 ;
• ⁢ ⁢ wherein ⁢ ⁢ KR 0 = n1 n1 + n2 ⁢ ⁢ and ⁢ ⁢ KR 1 = n3 n3 + n4 ;
• and ( 1 ⁢ a )
• substituting KR into formula:
• 17 DLY = k - ∑ i k ⁢ ⁢ KRi k × 100 ⁢ ( % ) ,
• wherein i is 1 to k;
• wherein k is the total number of wafer chips;
• and
• wherein KR is the probability that wafer chips fail.

A method of calculating a defect limited yield (DLY) comprising:

• determining the total number of wafer chips (m1);
• detecting defects in each said wafer chip;
• determining the total number of chips having said defects (m2);
• determining the total number of chips which fail due to a reason other than said defects (m3);
• classifying said wafer chips having defects using probable parameters in consideration of area, size, and number of said defects;
• determining the total number of wafer chips (m4) and the total number of wafer chips which fail (m5) when said wafer chips are classified according to each said probable parameter;
• calculating a probability (KR) that said wafer chips fail only due to said defects by substituting the data m1, m2, m3, m4, and m5 in the formula:
• 18 KR = 1 - 1 - KR 1 1 - KR 0 , ⁢ wherein ⁢ , KR 0 = m3 m1 - m2 ⁢ ⁢ and ⁢ ⁢ KR 1 = m5 m4 ;
• and
• substituting KR into formula:
• 19 DLY = k - ∑ i k ⁢ ⁢ KRi k × 100 ⁢ ( % )
• wherein i is 1 to k;
• wherein k is the total number of wafer chips;
• and
• wherein KR is the probability that wafer chips fail.

A system for calculating a probability of failure caused by defects only in inspected blocks in a wafer chip comprising:

• a defect detector for detecting defects in said inspected blocks in said chip;
• a controller for comparing data obtained by said defect detector and layout information of said inspected blocks;
• and
• a display unit for displaying information from said controller so that a process performer can monitor said displayed information.

A system for calculating a probability of failure caused only by defects in wafer chips comprising:

• a defect detector for detecting defects in each of said wafer chips;
• a controller for comparing data obtained by said defect detector and layout information of said wafer chips, said layout information being stored in advance;
• and
• a display unit for displaying information from said controller so that a process performer can monitor said displayed information.

A post management system comprising:

• a defect detector for detecting defects in wafer chips;
• a first storage for storing defect information obtained from said defect detector;
• an EDS inspecting unit for inspecting whether cell regions are turned on or off;
• a second storage for storing said on/off data obtained from said EDS inspecting unit;
• and
• a controller for comparing data from said first storage and said second storage with layout information of said wafer chips and creating a decision tree.