Method for fabricating semiconductor device capable of improving process margin of self align contact

Abstract

The present invention provides a method for fabricating a semiconductor device capable of minimizing losses of a gate electrode and a hard mask during a self align contact (SAC) formation process. For this effect, the present invention includes the steps of: forming a plurality of conductive patterns on a substrate; forming hard masks on the conductive patterns; forming an organic based dielectric layer on the substrate including the conductive patterns and the hard mask; forming an oxide based insulation layer on the organic based dielectric layer; etching selectively the insulation layer so as to expose the organic based dielectric layer allocated between the conductive patterns; and etching selectively the exposed organic based dielectric layer to form a contact hole that exposes the surfaces of the substrate between the conductive patterns with an O2 gas as a main etching gas.

Dependencies are inferred from the claim text.