Method for manufacturing semiconductor device of sub-micron or high voltage CMOS structure

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a barrier film in a field region of a semiconductor substrate;
• forming a first conductivity-type well region and a second conductivity-type well region;
• forming a gate insulating film on an entire surface of the semiconductor substrate;
• forming a plurality of contact holes in the gate insulating film;
• forming a conductive pattern inside each contact hole;
• forming a gate electrode on the gate insulating film between the conductive patterns;
• forming a lightly-doped first conductivity-type impurity region in the first conductivity-type well region at a first side of the gate electrode;
• forming a lightly-doped second conductivity-type impurity region in the second conductivity-type well region at a second side of the gate electrode;
• forming an insulating film on the semiconductor substrate to expose an upper portion of the conductive pattern and the gate electrode;
• and
• forming heavily-doped first and second conductivity-type impurity regions on the lightly-doped first and second conductivity-type impurity regions below the conductive pattern.

A semiconductor device, comprising:

• a semiconductor substrate;
• a first conductivity-type well region in the semiconductor substrate;
• a plurality of lightly-doped second conductivity-type impurity regions formed in opposing portions of the first conductivity-type well region;
• a plurality of heavily-doped second conductive-type impurity regions formed in the lightly-doped second conductivity-type impurity regions;
• a gate insulating film on the semiconductor substrate, the gate insulating film having a plurality of first contact holes exposing portions of the heavily-doped second conductivity-type impurity regions;
• a gate electrode on the gate insulating film, the gate electrode having upper and lower surfaces;
• an insulating layer on the gate insulating film having upper and lower surfaces, the upper and lower surfaces of the insulating layer are coplanar with upper and lower surfaces of the gate electrode, respectively;
• a plurality of second contact holes formed in the insulating layer, each of the second contact holes are concentric with each of the plurality of first contact holes;
• and
• a plurality of conductive patterns in the first and second pluralities of contact holes contacting the heavily-doped second conductivity-type impurity regions, the conductive patterns having an upper surface coplanar with the upper surfaces of the gate electrode and insulating layer.