Semiconductor memory device
OwnerKazunobu Kuwazawainventor
Life of this patent
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Abstract
A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved β ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.
Claims14
A method for forming a semiconductor device comprising:
- forming a pair of transfer MOS transistors controlled by a word line;
- and
- forming a pair of data retaining flip-flop circuits from serially connected load elements and drive MOS transistors;
- wherein the transfer MOS transistors are formed to have a threshold voltage greater than that of the drive MOS transistors.
A method for forming a semiconductor device comprising:
- forming a pair of transfer MOS transistors controlled by a word line;
- forming a pair of data retaining flip-flop circuits from serially connected load elements and drive MOS transistors;
- and
- forming a gate electrode of each of the transfer MOS transistors to have a lower impurity concentration than that of a gate electrode of each of the drive MOS transistors.
A method for forming a semiconductor device including an SRAM, comprising:
- forming a first transistor to include a gate electrode connected to a word line and to include a first end connected to a first bit line;
- forming a second transistor to include a gate electrode connected to the word line and to include a first end connected to a second bit line;
- forming a third transistor to include a gate electrode and to include a first end connected to a ground potential and a second end connected to a second end of the first transistor;
- forming a fourth transistor to include a gate electrode and to include a first end connected to the ground potential and a second end connected to a second end of the second transistor;
- forming a fifth transistor to include a gate electrode and to include a first end connected to a power supply and a second end connected to the second end of the first transistor;
- forming a sixth transistor to include a gate electrode and to include a first end connected to the power supply and a second end connected to the second end of the second transistor;
- forming the gate electrode of the third transistor and the gate electrode of the fifth transistor to each be connected to the second end of the second transistor;
- forming the gate electrode of the fourth transistor and the gate electrode of the sixth transistor to each be connected to the second end of the first transistor;
- and
- forming the first and second transistors to have a threshold voltage that is greater than a threshold voltage of the third and fourth transistors.
Dependencies are inferred from the claim text.