Method of fabricating dual threshold voltage n-channel and p-channel MOSFETs with a single extra masked implant operation

A method of forming a plurality of active regions on a substrate, comprising:

• forming isolation structures in the substrate, the isolation structures defining the plurality of active regions;
• patterning a first masking layer such that at least two first active regions are exposed and at least two second active regions are covered by the first masking layer;
• performing a p-well implant and a low Vtn implant into the exposed first active regions;
• removing the first masking layer and patterning a second masking layer such that the at least two first active regions are covered and the at least two second active regions are exposed;
• performing an n-well implant and a high Vtp implant into the exposed active regions;
• removing the second masking layer and patterning a third masking layer such that at least one of the at least two first active regions is exposed, and at least one of the at least two second active regions is exposed;
• and
• performing a high Vtn implant into the exposed active regions.

A method of forming transistors, comprising:

• forming a first p-well, and a second p-well;
• implanting a p-type dopant, at a first dose and energy, into the first and second p-wells;
• forming a first n-well, and a second n-well;
• implanting an n-type dopant, at a second dose and energy, into the first and second n-wells;
• implanting a p-type dopant, at a third dose and energy, into the second p-well and the second n-well;
• and
• forming a first NFET having a first threshold voltage in the first p-well, a second NFET having a second threshold voltage in the second p-well, a first PFET having a third threshold voltage, in the first n-well, and a second PFET having a fourth threshold in the second n-well;
• wherein the first and second threshold voltages are different from each other, and the third and fourth threshold voltages are different from each other.

A manufacturing process, comprising:

• forming a first, a second, a third, and a fourth active region in a substrate;
• patterning a first mask layer such that first and second active regions are exposed and third and fourth active regions are covered by the first mask layer;
• performing a p-well implant and a low Vt NFET implant into the exposed first and second active regions;
• removing the first mask layer and patterning a second mask layer such that the first and second active regions are covered and the third and fourth active regions are exposed;
• performing an n-well implant and a high Vt PFET implant into the exposed third and fourth regions;
• removing the second mask layer and patterning a third mask layer such that the first and third active regions are covered, and the second and fourth active regions are exposed;
• and
• implanting a p-type dopant into the exposed second and fourth active regions.

A method of forming transistors, comprising:

• forming a first p-well, and a second p-well;
• implanting a p-type dopant, at a first dose and energy, into the first and second p-wells;
• forming a first n-well, and a second n-well;
• implanting an n-type dopant, at a second dose and energy, into the first and second n-wells;
• implanting an n-type dopant, at a third dose and energy, into the first p-well and the first n-well;
• and
• forming a first NFET having a first threshold voltage in the first p-well, a second NFET having a second threshold voltage in the second p-well, a first PFET having a third threshold voltage, in the first n-well, and a second PFET having a fourth threshold in the second n-well;
• wherein the first and second threshold voltages are different from each other, and the third and fourth threshold voltages are different from each other.