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US 2003/0119236 A1Published application
Method of fabricating enhanced EPROM structures with accentuated hot electron generation regions
AssigneeIntersil Americas Inc.
InventorMichael David Church
Life of this patent
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Abstract
An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.
Claims21
A process for making a semiconductor device comprising the steps of:
- performing a LOCOS operation on an epitaxial layer of a semiconductor substrate to define an active region having a predefined boundary;
- implanting a first dopant into the epitaxial layer within the active region to create a well of a first type of conductivity;
- implanting the first dopant into the well to create at least a first region;
- depositing a polysilicon layer over the active region;
- doping the polysilicon layer to create a poly semiconductor layer of a second type of conductivity;
- patterning the poly semiconductor layer to create a poly gate over the first region and well;
- performing an ion implant of the second type conductivity between the LOCOS regions and the poly gate to create first and second lightly doped regions, the first and second lightly doped regions being separated by a channel region beneath the poly gate;
- depositing an oxide layer over the poly gate and active region;
- etching the oxide layer to create side spacers on each side of the poly gate;
- and
- implanting a heavy dose of the second type of dopant between the LOCOS regions and the side spacers to create source and drain regions, the source and drain regions being separated by the channel region.
8 more elements
A process for making a semiconductor device comprising the steps of:
- performing a LOCOS operation on an epitaxial layer to define an active region;
- using a first reticle to create a pattern for implanting a first dopant into the epitaxial layer within the active region to create a well of a first type of conductivity;
- using a second reticle to create a pattern for implanting with the first type of dopant into the well to create first and second regions;
- depositing a polysilicon layer over the active region;
- heavily doping with a second dopant the polysilicon layer to create a poly semiconductor layer of a second type of conductivity;
- patterning the poly semiconductor layer to create a poly gate;
- using a third reticle to create a pattern for lightly doping with a second dopant the active region between the LOCOS regions and the poly gate;
- depositing an oxide layer over the poly gate and active region;
- etching the oxide layer to create side spacers on each side of the poly gate;
- and
- using the third reticle to create a pattern for heavily doping with the second dopant the active region between the LOCOS regions and the side spacers.
8 more elements
Dependencies are inferred from the claim text.