Ferroelectric-type nonvolatile semiconductor memory and operation method thereof

A ferroelectric-type nonvolatile semiconductor memory comprising;

• (A) a bit line,
• (B) transistors for selection in the number of N wherein N≧2,
• (C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein M≧2, and
• (D) plate lines in the number of M,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• the first electrodes are in common in each memory unit,
• the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection wherein n=1, 2 . . . N, and
• in the n-th memory unit, the second electrode of the m-th memory cell is connected to the m-th plate line common to the memory units wherein m=1, 2 . . . M.

A ferroelectric-type nonvolatile semiconductor memory comprising;

• (A) a bit line,
• (B) transistors for selection in the number of 2N wherein N≧1,
• (C) memory units in the number of 2N, each memory unit comprising memory cells in the number of M wherein M≧2, and
• (D) plate lines in the number of M,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• the first electrodes are in common in each memory unit,
• the common first electrode in the (2n−1)-th memory unit is connected to the bit line through the (2n−1)-th transistor for selection wherein n=1, 2 . . . N,
• the common first electrode in the 2n-th memory unit is connected to the bit line through the 2n-th transistor for selection, and
• the m-th memory cell constituting the (2n−1)-th memory unit and the m-th memory cell constituting the 2n-th memory unit share the second electrode, and the shared m-th second electrode is connected to the m-th plate line wherein m=1, 2 . . . M.

A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit,

• the first memory unit comprising;
• (A-1) a first bit line,
• (B-1) first transistor or transistors for selection in the number of N wherein N≧1,
• (C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein M≧2, and
• (D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and
• the second memory unit comprising;
• (A-2) a second bit line,
• (B-2) second transistor or transistors for selection in the number of N,
• (C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M, and
• (D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit,
• in which
• the first sub-memory unit is stacked on the second sub-memory unit through an insulating interlayer,
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N;
• the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection;
• and the second electrode of the m-th-place first memory cell is connected to the common m-th plate line wherein m=1, 2 . . . M, and
• in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are in common in the n-th-place second sub-memory unit;
• the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection;
• and the second electrode of the m-th-place second memory cell is connected to the common m-th plate line.

A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit,

• the first memory unit comprising;
• (A-1) a first bit line,
• (B-1) first transistor or transistors for selection in the number of N wherein N≧1,
• (C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein M≧2, and
• (D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and
• the second memory unit comprising;
• (A-2) a second bit line,
• (B-2) second transistor or transistors for selection in the number of N,
• (C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M, and
• (D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N;
• and the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection,
• in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are in common in the n-th-place second sub-memory unit;
• and the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection, and
• the m-th-place first memory cell constituting the n-th-place first sub-memory unit in the first memory unit and the m-th-place second memory cell constituting the n-th-place second sub-memory unit in the second memory unit share the second electrode, and the shared m-th second electrode is connected to the m-th plate line wherein m=1, 2 . . . M.

A ferroelectric-type nonvolatile semiconductor memory comprising;

• (A) a bit line,
• (B) a transistor for selection,
• (C) a memory unit comprising memory cells in the number of M wherein M≧2, and
• (D) plate lines in the number of M,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• the first electrodes of the memory cells are in common in each memory unit,
• the common first electrode is connected to the bit line through the transistor for selection, and
• the second electrode constituting the memory cell is connected to the plate line, and
• further in which
• (E) a signal detective circuit for detecting a change in potential of the common first electrode and transmitting a detection result to the bit line as a current or a voltage is provided.

A ferroelectric-type nonvolatile semiconductor memory comprising;

• (A) a bit line,
• (B) a transistor for writing-in,
• (C) a memory unit comprising memory cells in the number of M wherein M≧2, and
• (D) plate lines in the number of M,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• the first electrodes of the memory cells are in common in each memory unit,
• the common first electrode is connected to the bit line through the transistor for writing-in, and
• the second electrode constituting the memory cell is connected to the plate line, and
• the ferroelectric-type nonvolatile semiconductor memory further having;
• (E) a transistor for detection, and
• (F) a transistor for read-out,
• and further in which one end of the transistor for detection is connected to a wiring having a predetermined potential, and the other end thereof is connected to the bit line through the transistor for read-out, and
• when data stored in the memory cell is read out, the transistor for read-out is brought into a continuity state, and the operation of the transistor for detection is controlled by means of a potential that takes place in the common first electrode on the basis of the data stored in the memory cell.

A ferroelectric-type nonvolatile semiconductor memory comprising;

• (A) a bit line,
• (B) a transistor for writing-in,
• (C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein N≧2 and M≧2,
• (D) transistors for selection in the number of N, and
• (E) plate lines in the number of M, each plate line being common to the memory cells each of which constitutes each of the memory units in the number of N,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• the first electrodes are in common in each memory unit,
• the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection and the transistor for writing-in wherein n=1, 2 . . . N, and
• the second electrode constituting the m-th memory cell is connected to the common m-th plate line wherein m=1, 2 . . . M,
• the ferroelectric-type nonvolatile semiconductor memory further comprising;
• (F) a transistor for detection, and
• (G) a transistor for read-out,
• and further in which one end of the transistor for detection is connected to a wiring having a predetermined potential, and the other end thereof is connected to the bit line through the transistor for read-out, and
• when data stored in the memory cell constituting the n-th memory unit is read out, the n-th transistor for selection and the transistor for read-out are brought into a continuity state, and the operation of the transistor for detection is controlled by means of a potential that takes place in the common first electrode on the basis of the data stored in the memory cell.

An operation method of a ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit,

• the first memory unit comprising;
• (A-1) a first bit line,
• (B-1) first transistor or transistors for selection in the number of N wherein N≧1,
• (C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein M≧2, and
• (D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and
• the second memory unit comprising;
• (A-2) a second bit line,
• (B-2) second transistor or transistors for selection in the number of N,
• (C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M, and
• (D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N;
• the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection;
• and the second electrode of the m-th-place first memory cell is connected to the common m-th-place plate line wherein m =1, 2 . . . M, and
• in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are common in the n-th-place second sub-memory unit;
• the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection;
• and the second electrode of the m-th-place second memory cell is connected to the common m-th-place plate line,
• said method comprising performing reading out data stored in the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line and re-writing data into the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line by performing potential rising and potential falling once each.

A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit,

• the first memory unit comprising;
• (A-1) a first bit line,
• (B-1) first transistor or transistors for selection in the number of N wherein N≧1,
• (C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein M≧2, and
• (D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and
• the second memory unit comprising;
• (A-2) a second bit line,
• (B-2) second transistor or transistors for selection in the number of N,
• (C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M,
• (D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N;
• the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection;
• and the second electrode of the m-th-place first memory cell is connected to the common m-th-place plate line wherein m =1, 2 . . . M,
• in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are in common in the n-th-place second sub-memory unit;
• the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection;
• and the second electrode of the m-th-place second memory cell is connected to the common m-th-place plate line,
• and further wherein latch circuits in the number of P are provided between the first bit line and the second bit line for latching data stored in the first memory cell and second memory cell.

An operation method of a ferroelectric-type nonvolatile semiconductor memory comprising;

• (A) a bit line,
• (B) transistors for selection in the number of N wherein N≧2,
• (C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein M≧2, and
• (D) plate lines in the number of M,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• the first electrodes are in common in each memory unit,
• the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection wherein n=1, 2 . . . N, and
• in the n-th memory unit, the second electrode of the m-th memory cell is connected to the m-th plate line common to the memory units wherein m=1, 2 . . . M,
• said method comprising performing reading out data stored in the memory cells sharing the plate line in the memory units in the number of N and re-writing data into the memory cells sharing the plate line in the memory units in the number of N by performing potential rising and potential falling once each.

An operation method of a ferroelectric-type nonvolatile semiconductor memory comprising;

• (A) a bit line,
• (B) transistors for selection in the number of N wherein N≧2,
• (C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein M≧2, and
• (D) plate lines in the number of M,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• the first electrodes are in common in each memory unit,
• the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection wherein n=1, 2 . . . N, and
• in the n-th memory unit, the second electrode of the m-th memory cell is connected to the m-th plate line common to the memory units wherein m=1, 2 . . . M,
• said method comprising reading out data stored in the memory cells sharing the plate line in the memory units in the number of N by first providing the plate line with a pulse and then consecutively selecting the transistors for selection in the number of N.

A ferroelectric-type nonvolatile semiconductor memory comprising;

• (A) a bit line,
• (B) transistors for selection in the number of N wherein N≧2,
• (C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein M≧2, and
• (D) plate lines in the number of M,
• in which
• each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
• the first electrodes are in common in each memory unit,
• the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection wherein n=1, 2 . . . N, and
• in the n-th memory unit, the second electrode of the m-th memory cell is connected to the m-th plate line common to the memory units wherein m=1, 2 . . . M,
• and further in which
• latch circuits in the number of at least N are connected to the bit line for latching data stored in the memory cells.