Method of improving surface planarity prior to MRAM bit material deposition
AssigneeMicron Technology, Inc.
InventorsDonald L. Yates, Joel A. Drewes
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Abstract
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
Claims39
A method of fabricating a portion of a memory cell, said method comprising:
- forming an insulating layer over a substrate;
- forming a trench in said insulating layer;
- lining said trench with a first barrier layer to a first conductive material;
- forming said first conductive layer in said trench;
- planarizing an upper surface of said layers;
- forming a layer of a second conductive material over said layers;
- and
- removing an upper portion of said second conductive layer to flatten an upper surface of said second conductive layer while leaving a lower portion of said second conductive layer intact over said first conductive layer.
A method of fabricating a portion of a memory cell, said method comprising:
- forming a first conductor in a trench provided in an insulating layer;
- flattening an upper surface of said insulating layer and said first conductor, said flattening leaving a roughened upper surface of said conductor;
- forming a material layer over said flattened upper surface of said insulating layer and said first conductor;
- and
- flattening an upper portion of said material layer while leaving intact a lower portion of said material layer over said insulating layer and said first conductor.
A method of fabricating a portion of a memory cell, said method comprising:
- forming a first conductor layer over an insulating layer of a substrate;
- flattening an upper surface of said layers, said flattening leaving a roughened upper surface of said conductive layer;
- forming a material layer over said flattened upper surface of said layers;
- and
- flattening an upper portion of said material layer while leaving intact a lower portion of said material layer over said conductive layer.
A magnetic random access memory structure comprising:
- a plurality of longitudinally extending planarized conductive lines formed over an insulating layer of a semiconductor substrate;
- respective first magnetic layers over said conductive lines;
- respective second magnetic layers over said first magnetic layers;
- at least one contact;
- and
- a planarized conductive material layer formed between said planarized conductive lines and said first magnetic layers.
A memory device comprising:
- at least one magnetic random access memory cell, said magnetic random access memory cell comprising a first ferromagnetic layer formed over a first planarized conductor, a second ferromagnetic layer formed over said first ferromagnetic layer, a nonmagnetic layer between said first and second ferromagnetic layers, and a planarized conductor layer provided between said first conductor and said first ferromagnetic layer.
A processor-based system, comprising:
- a processor;
- and
- an integrated circuit coupled to said processor, said integrated circuit including a plurality of magnetic random access memory cells, each of said magnetic random access memory cells including a first ferromagnetic layer formed over a first planarized conductor, a second ferromagnetic layer formed over said first ferromagnetic layer, a nonmagnetic layer between said first and second ferromagnetic layers, and a planarized conductor layer provided between said first conductor and said first ferromagnetic layer.
Dependencies are inferred from the claim text.