Back to results
US 2003/0116786 A1Published application
Semiconductor memory test device
AssigneeHynix Semiconductor Inc.
InventorKee Teok Park
Life of this patent
Estimating the term…
Abstract
A semiconductor memory test device is capable of reducing the test time and increasing test reliability by applying an effective stress in a burn-in level or a wafer level. The semiconductor memory test device controls a sense amplifier using an additional sense amplifier driving signal when a 2rb pattern stress is applied. Therefore, the semiconductor memory test device applies a uniform stress by applying the constant supply voltage to a cell corresponding to the entire wordlines.
Claims10
A semiconductor memory test device, comprising:
- a test mode decoder for decoding an inputted address signal to produce a wordline driving signal and a sense amplifier driving signal;
- and
- a driving unit for controlling said sense amplifier to enable all the wordlines when said sense amplifier is enabled, depending on said sense amplifier driving signal.
A semiconductor memory test device, comprising:
- a test mode decoder for decoding inputted address signals to produce a wordline driving signal and a sense amplifier driving signal;
- a sense amplifier control unit for decoding the wordline driving signal to produce a wordline driver driving select signal, and enabling all the wordlines when said sense amplifier is enabled, depending on said sense amplifier driving signal;
- a sub-hole for inverting the wordline driver driving select signal and the sense amplifier control signal;
- a sub X-decoder for enabling a selected wordline depending on the wordline driver driving select signal;
- and
- a sense amplifier enabled depending on the sense amplifier control signal.
3 more elements
Dependencies are inferred from the claim text.