Semiconductor memory device having COB structure and method of fabricating the same

A method of fabricating a semiconductor device, comprising:

• forming a plurality of gate patterns on a substrate, wherein the plurality of gate patterns is extended in a first direction and defines a plurality of spatial lanes therebetween;
• forming rows of buried contact pads and direct contact pads on the spatial lanes, wherein the rows of the buried contact pads are formed on every second spatial lane, and wherein the rows of the direct contact pads are formed on every second spatial lane;
• forming a lower insulating film on the buried contact pads, the direct contact pads and the gate patterns;
• and
• forming a plurality of bit line patterns on the lower insulating film, wherein the plurality of bit line patterns is extended in a second direction, wherein the bit line patterns have a first width over the spatial lanes on which the buried contact pads are formed, wherein the bit line patterns have a second width over the spatial lanes on which the direct contact pads are formed, and wherein the second width is greater than the first width.

A semiconductor device, comprising:

• first conductive regions and second conductive regions on a substrate;
• a lower insulating film on the substrate;
• intermediate strips on a portion of the lower insulating film;
• mask-defining patterns on the other portion of the lower insulating film;
• a mask on the intermediate strips, wherein the mask overlaps the second conductive regions in plan view;
• an upper insulating film on the mask;
• and
• hollows formed through the upper insulating film, the lower insulating film and the mask-defining patterns, wherein the hollows expose the first conductive regions, wherein each of the hollows comprises an intermediate hollow, wherein the intermediate hollow is surrounded by the mask, wherein the diameter of the intermediate hollow is decreased gradually in a direction to the substrate.