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US 2003/0112565 A1Published application
Polarity reversal tolerant electrical circuit for ESD protection
AssigneeKoninklijke Philips Electronics N.V.
InventorsQing He, DC Sessions
Life of this patent
Estimating the term…
Abstract
An ESD protection circuit is provided which offers full protection for sub micron CMOS technology integrated circuits that does not have a latchup problem as in silicon controller rectifier circuits. The primary ESD protection transistor within the circuit channeling deleterious ESD currents away from the electrical circuit using snapback conduction while additionally enabling bipolar operation of the electrical circuit.
Claims22
An ESD protection circuit comprising:
- a first voltage input port;
- a second voltage input port;
- an ESD protection circuit including a primary transistor comprising a first port a second port and a control port for controlling current flow between the first port and the second port, the first port and the second port coupled electrically between the first voltage input port and the second voltage input port;
- and,
- a polarity independent control circuit for providing a same voltage at the control port of the primary transistor within the ESD protection circuit for either of the polarities of the voltage applied across the first voltage input port and the second voltage input port.
2 more elements
An ESD protection circuit comprising:
- a first voltage input port;
- a second voltage input port;
- a common bulk node;
- a primary ESD protection transistor having a first port coupled to the first voltage input port, a second port coupled to the second voltage input port, and a control port coupled to the common bulk node for controlling current flow between the first port and the second port;
- a secondary ESD protection transistor having a first port electrically coupled to the first voltage input port, a second port coupled to the second voltage input port, and a control port coupled to the common bulk node for controlling current flow between the first port and the second port;
- a forward bias transistor having a first port electrically coupled to the first voltage input port, a second port coupled to the common bulk, and a control port electrically coupled to the second voltage input port for controlling current flow between the first port and the second port;
- and
- a reverse bias transistor having a first port coupled to the common bulk node a second port coupled to the second voltage input port and a control port electrically coupled to the first port of the forward bias transistor for controlling current flow between the first port and the second port,
- wherein the primary, secondary, forward bias, and reverse bias transistors sharing the same common bulk node.
6 more elements
A method of offering ESD protection comprising the steps of:
- provide a control circuit for providing a voltage output within a known range in response to an applied voltage potential independent of the voltage potential polarity;
- coupling a power source across a primary ESD protection transistor having a minimum holding voltage, the ESD protection transistor having a control port for receiving the voltage output;
- when an ESD event transient voltage above the minimum holding voltage occurs, performing snapback conduction on the primary ESD protection transistor,
- wherein the ESD event transient voltage being above the ESD protection transistor holding voltage enables snapback current to flow through the primary ESD protection transistor
1 more element
Dependencies are inferred from the claim text.