Packing device for embedding a capacitor on chip
AssigneeSilicon Integrated Systems Corp.
InventorsWei-Feng Lin, Ming-Huan Lu, Chung-Ju Wu
Life of this patent
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Abstract
The present invention discloses a packaging device, which embeds a capacitor on a chip so as to effectively filter out the current noise. The packaging device of the invention includes a substrate, a chip, and at least one capacitor. The chip is configured on the substrate and includes at least one power line and ground line. The at least one capacitor is configured on the surface of the chip and electrically connected to the power line and ground line. Furthermore, the invention can configure at least one capacitor on a carrier board attached on the surface of the chip, and the at least one capacitor is electrically connected to the power line and ground line through circuits of the carrier board.
Claims10
A packaging device for embedding a capacitor on chip, comprising:
- a substrate;
- a chip placed on said substrate, said chip including at least one power line and ground line;
- and
- at least one capacitor embedded on said chip and electrically connected to said power line and ground line.
A packaging device for embedding a capacitor on chip, comprising:
- a substrate;
- a chip placed on said substrate, said chip including at least one power line and ground line;
- a carrier socket placed on said chip;
- and
- at least one capacitor placed on said carrier socket and electrically connected to said power line and ground line.
Dependencies are inferred from the claim text.