Semiconductor devices and methods of fabricating the same

A semiconductor device, comprising:

• an isolation layer disposed in a substrate of first conductivity type, the isolation layer comprising an outline defining an active region of the substrate;
• a gate pattern crossing the active region;
• source and drain regions of second conductivity type within the active region of the substrate, the source region at one side of the gate pattern and the drain region at a side of the gate pattern opposite the one side;
• and
• a salicide layer covering each of the source and drain regions,
• the isolation layer comprising a recess that exposes a portion of the substrate of first conductivity type adjacent one of the source and drain regions of second conductivity type;
• and
• the salicide layer having a portion that extends beyond the one of the source and drain regions of second conductivity type to cover the portion of the substrate of first conductivity type exposed by the recess.

A semiconductor device, comprising:

• a substrate having N-type and P-type regions;
• an isolation layer disposed in a predetermined region of the substrate, the isolation layer comprising an outline for defining a first active region in the N-type region, the outline of the isolation layer further defining a second active region in the P-type region;
• first and second gate patterns crossing the first and second active regions, respectively;
• P-type source and drain regions in the first active region at opposite respective sides of the first gate pattern;
• N-type source and drain regions in the second active region at opposite respective sides of the second gate pattern;
• and
• salicide covering the N-type source and drain regions and the P-type source and drain regions;
• the isolation layer comprising a first recess that exposes a portion of the N-type region of the substrate adjacent to one of the P-type source and drain regions;
• the isolation layer further comprising a second recess that exposes a portion of the P-type region of the substrate adjacent to one of the N-type source and drain regions;
• the salicide comprising a layer thereof with a portion that extends beyond the one of the N-type source and drain regions and covers the portion of the P-type region of the substrate facing the first recess;
• and
• the salicide layer further comprising another portion that extends beyond the one of the P-type source and drain regions and covers the portion of the N-type region of the substrate exposed by the second recess.

A method of fabricating a semiconductor substrate, comprising:

• forming an isolation layer in a substrate of first conductivity type, the isolation layer formed with an outline to define an active region;
• diffusing impurities of second conductivity type in a predetermined region of the active region to form an impurity diffused region;
• recessing a region of the device isolation layer and exposing a portion of the first conductivity type material under the impurity diffused region;
• and
• forming a salicide layer covering the impurity diffused region and covering the portion of the first conductivity type material exposed by the recess.

A method of fabricating a semiconductor device, comprising:

• forming a device isolation layer in a predetermined region of a substrate of first conductivity type to define an outline to an active region;
• forming a gate pattern crossing the active region;
• forming a source/drain region of second conductivity type in the active region at both sides of the gate pattern;
• patterning the device isolation layer and forming a recess that exposes a portion of the substrate of first conductivity type, the portion exposed adjacent to the source/drain region of second conductivity type at one side of the gate pattern;
• and
• siliciding a surface of the source/drain region of second conductivity type and a surface of the substrate of first conductivity type exposed by the recess.

A method of fabricating a semiconductor device, comprising:

• forming a device isolation layer in a semiconductor substrate of N-type and P-type regions;
• the device isolation layer formed with outlines defining first and second active regions in the N-type and P-type regions, respectively;
• forming first and second gate patterns crossing the first and second active regions, respectively;
• forming a P-type source/drain region in the first active region at both sides of the first gate pattern;
• forming an N-type source/drain region in the second active region at both sides of the second gate pattern;
• patterning the device isolation layer to form first and second recesses;
• the first recess to expose a portion of the N-type region of the substrate adjacent to the P-type source/drain region at one side of the first gate pattern;
• the second recess to expose a portion of the P-type region of the substrate adjacent to the N-type source/drain region at one side of the second gate pattern;
• and
• siliciding the exposed portions of the N-type and P-type regions facing respective first and second recesses;
• and
• siliciding surfaces of the N-type and P-type source/drain regions of respective second and first active regions.