Memory cell with trench transistor

Memory cell with a storage transistor comprising a gate electrode (4) at a top surface of a semiconductor body (1) or semiconductor layer, which is disposed between a source zone (2) and a drain zone (2) in a trench that is installed in the semiconductor material of the semiconductor body or layer and that exhibits identical cross-sections transverse to a longitudinal direction, at least section by section, whereby the source zone (2) and the drain zone (3) are formed in the semiconductor material by doping from the top surface to a respective junction (14), and the gate electrode is isolated from the semiconductor material by a dielectric layer (9) which is constructed as a storage medium, characterized in that the depth (25) of the trench, as measured between the junctions (14) and a deepest point of the trench relative to the plane of the top surface in the perpendicular vertical direction relative to a plane of the top surface of the semiconductor body (1) or layer, is at most half as large as the spacing (24) of the walls of the trench at the height of the junctions (14).

Memory cell with a storage transistor comprising a gate electrode (4) at a top surface of a semiconductor body (1) or semiconductor layer, which is disposed between a source zone (2) and a drain zone (2) in a trench that is installed in the semiconductor material of the semiconductor body or layer and that exhibits identical cross-sections transverse to a longitudinal direction, at least section by section, whereby the source zone (2) and the drain zone (3) are formed in the semiconductor material by doping from the top surface to a respective junction (14), and the gate electrode is isolated from the semiconductor material by a dielectric layer (9) which is constructed as a storage medium, characterized in that the junctions (14) abut the walls of the trench in a region wherein the walls of the trench within a cross-section situated perpendicular to the longitudinal direction have a curve radius which is at most 10% larger than a smallest value assumed by the curve radius at the trench wall.

Memory cell with a storage transistor comprising a gate electrode (4) at a top surface of a semiconductor body (1) or semiconductor layer, which is disposed between a source zone (2) and a drain zone (2) in a trench that is installed in the semiconductor material of the semiconductor body or layer and that exhibits identical cross-sections transverse to a longitudinal direction, at least section by section, whereby the source zone (2) and the drain zone (3) are formed in the semiconductor material by doping, and the gate electrode is isolated from the semiconductor material by a dielectric layer (9) that includes a storage layer (11) between boundary layers (10, 12), characterized in that the depth of the trench with respect to a region in which charge carriers of the storage layer (11) are neutralized in an erase operation is selected such that in a program operation a component of an electrical field that acts on the charge carriers, which component is aligned parallel to the tangent at a wall or at the bottom of the trench and perpendicular to the longitudinal direction, is at a maximum in the same region.