Non-volatile semiconductor memory device and manufacturing method thereof

A non-volatile semiconductor memory device, comprising:

• a semiconductor substrate of a first conductivity type having a main surface;
• first and second impurity diffusion layers of a second conductivity type of a first memory cell formed spaced from each other at the main surface of said semiconductor substrate;
• a floating gate of said first memory cell formed on a region between said first and second impurity diffusion layers with a first insulating film interposed;
• an access gate of said first memory cell formed adjacent to said floating gate on a region between said first and second impurity diffusion layers with a second insulating film interposed;
• a control gate of said first memory cell formed on said floating gate with a third insulating film interposed;
• another floating gate of a second memory cell provided at a position adjacent to said floating gate of said first memory cell with said first impurity diffusion layer positioned therebetween;
• and
• another control gate of said second memory cell formed on said another floating gate with a fourth insulating film interposed.

A non-volatile semiconductor memory device, comprising:

• a semiconductor substrate of a first conductivity type having a main surface;
• first and second impurity diffusion layers of a second conductivity type formed spaced from each other at the main surface of said semiconductor substrate;
• a floating gate formed on a region between said first and second impurity diffusion layers with a first insulating film interposed;
• an access gate having a sidewall shape formed adjacent to said floating gate in a region between said first and second impurity diffusion layers with a second insulating film interposed;
• and
• a control gate formed on said floating gate with a third insulating film interposed.

A method of manufacturing a non-volatile semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, first and second impurity diffusion layers of a second conductivity type formed spaced from each other at the main surface of said semiconductor substrate, a floating gate formed adjacent to said first impurity diffusion layer with a first insulating film on said main surface of said semiconductor substrate interposed, an access gate formed adjacent to said floating gate and said second impurity diffusion layer with a second insulating film on said main surface of said semiconductor substrate interposed, a control gate formed on said floating gate with a third insulating film interposed, comprising the steps of:

• forming a pattern of said floating gate including first conductive film on said main surface of a semiconductor substrate with said first insulating film interposed;
• forming a first impurity diffusion layer of a second conductivity type, using said pattern of said floating gate as a mask;
• forming said second insulating film and a pattern of said access gate including second conductive film;
• and
• forming a second impurity diffusion layer of a second conductivity type, using said pattern of said access gate as a mask.