Semiconductor device having memory cell and peripheral circuitry with dummy electrode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYasuhiro Araki, Satoshi Shimizu
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Abstract
A semiconductor device includes: a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane; a floating gate electrode formed on semiconductor substrate in the memory cell section; a control gate electrode laminated thereabove; a gate electrode as a peripheral circuit electrode formed in one-layer-structure on semiconductor substrate in the peripheral circuit section; a first dummy electrode formed in the peripheral circuit section so as to have approximately same thickness as floating gate electrode; and a second dummy electrode laminated thereabove so as to have approximately same thickness as control gate electrode.
Claims8
A semiconductor device comprising:
- a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane;
- a floating gate electrode formed in one-layer-structure on said semiconductor substrate in said memory cell section;
- a control gate electrode laminated above said floating gate electrode;
- a peripheral circuit electrode formed in one-layer-structure on said semiconductor substrate in said peripheral circuit section;
- a first dummy electrode formed on said semiconductor substrate in said peripheral circuit section so as to have approximately same thickness as said floating gate electrode;
- and
- a second dummy electrode laminated above said first dummy electrode so as to have approximately same thickness as said control gate electrode.
A semiconductor device comprising:
- a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane;
- a floating gate electrode formed on said semiconductor substrate in said memory cell section;
- a control gate electrode laminated above said floating gate electrode;
- a peripheral circuit electrode formed in one-layer-structure on said semiconductor substrate in said peripheral circuit section;
- a contact receiving portion formed on said semiconductor substrate in said peripheral circuit section, and connected to said peripheral circuit electrode;
- and
- a third dummy electrode formed between said contact receiving portion and said semiconductor substrate.
A fabrication method for a semiconductor device which comprises a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane;
- wherein said memory cell section having a floating gate electrode and a control gate electrode;
- wherein said peripheral circuit section having a gate electrode in one-layer-structure and dummy electrodes in two-layer-structure;
- comprising the following steps:
- a first conductive layer forming step of collectively forming a first conductive layer including a portion to be served as a floating gate electrode in a memory cell section, across said memory cell section and said peripheral circuit section;
- a second conductive layer forming step of collectively forming a second conductive layer including a portion to be served as a control gate electrode laminated above said floating gate electrode in said memory cell section above said first conductive layer, across said memory cell section and said peripheral circuit section;
- a first conductive layer patterning step of patterning not only said floating gate electrode on said first conductive layer at a portion thereof located in said memory cell section, but also said first dummy electrode on said first conductive layer at a portion thereof located in said peripheral circuit section;
- a second conductive layer patterning step of patterning not only said control gate electrode on said second conductive layer at a portion thereof located in said memory cell section, but also said second dummy electrode on said second conductive layer at a portion thereof located in said peripheral circuit section;
- and
- a step of forming interlayer insulating film to cover said memory cell section and said peripheral circuit section collectively.
Dependencies are inferred from the claim text.