Ultra linear high speed operational amplifier output stage

An operational amplifier output stage, comprising:

• a pre-driver sub-stage having a plurality of transistors configured as translinear loops such that there is minimal net signal loss or signal attenuation in the pre-driver sub-stage;
• a final sub-stage coupled to, and biased by currents from, the pre-driver sub-stage, operable to provide minimal cross-over distortion;
• and
• a localized feedback circuitry and inherent RHPZ in the output stage operable to extend bandwidth.

An operational amplifier output stage, comprising:

• a first voltage supply rail Vcc connected to a first node;
• two connection terminals to an input stage, a first terminal connected to a second node for receiving a positive portion of an input signal and a second terminal connected to a sixth node for receiving a negative portion of an input signal;
• a first pre-driver sub-stage circuit coupled at the second node, the first pre-driver sub-stage circuit further comprising:
• a first transistor having its emitter coupled to the first voltage supply rail Vcc at the first node, and its base coupled at the second node;
• a second transistor having its emitter coupled to the second node and its base coupled to a third node;
• a third transistor having its base and collector coupled to the third node;
• a fourth transistor having its collector and base being coupled to a fourth node, and its emitter coupled to the first voltage supply rail Vcc at the first node;
• a second voltage supply rail Vee coupled to a fifth node;
• a second pre-driver sub-stage circuit coupled to the sixth node, the second pre-driver sub-stage circuit further comprising:
• a fifth transistor having its emitter coupled to the second voltage supply rail Vee at the fifth node, and its base coupled to the sixth node;
• a sixth transistor having its emitter coupled to the sixth node, its base coupled to a seventh node, and its collector coupled to the second node;
• a seventh transistor having its base and collector coupled to a seventh node;
• and its emitter coupled to an eighth node;
• an eighth transistor having its collector and base being coupled to the eighth node, and its emitter coupled to the second voltage supply rail Vee at the fifth node;
• a cross connection between the second transistor's collector and the sixth transistor's emitter at the sixth node, and the second transistor's emitter and the sixth transistor's collector at the second node, the cross connection resulting in a proportion of any error current flowing into the second transistor's emitter and sixth transistor's emitter to flow out through the second transistor's collector and the sixth transistor's collector into the base of the first transistor and the base of the fifth transistor;
• a first current source coupled between the first voltage supply rail Vcc at the first node and the second node;
• a second current source coupled between the first voltage supply rail Vcc at the first node and the seventh node;
• a third current source coupled between the second voltage supply rail Vee at the fifth node and at the third node;
• a fourth current source coupled between the second voltage supply rail Vee at the fifth node and the sixth node;
• a final sub-stage, comprising:
• a first final sub-stage circuit further conditioning the positive portion of the current signal provided by the first pre-driver sub-stage circuit, the first final sub-stage circuit comprising:
• a ninth transistor having its emitter coupled to the first transistor's collector at a ninth node, and its base and collector coupled to a tenth node;
• a tenth transistor having its base coupled to the ninth node, and its collector coupled to the first voltage supply Vcc rail at the first node;
• a second final sub-stage circuit further conditioning the negative portion of the current signal, provided by the second pre-driver sub-stage circuit, the second final sub-stage circuit comprising:
• an eleventh transistor having its emitter coupled to the fifth transistor's collector at an eleventh node, its base and collector coupled to the ninth transistor's base and collector at the tenth node;
• a twelfth transistor having its base coupled to the eleventh node, and its collector coupled to the second voltage supply rail Vee at the fifth node;
• a twelfth node interconnecting the tenth transistor's emitter with the twelfth transistor's emitter;
• and
• an output terminal coupled to the twelfth node.

An operational amplifier output stage, comprising:

• a first voltage supply rail Vcc connected to a first node;
• two connection terminals to an input stage, a first terminal connected to a second node for receiving a positive portion of a current signal and a second terminal connected to a sixth node for receiving a negative portion of a current input signal;
• a first pre-driver sub-stage circuit coupled at the second node, the first pre-driver sub-stage circuit further comprising:
• a first transistor having its emitter coupled to the first voltage supply rail Vcc at the first node, and its base coupled at the second node;
• a second transistor having its emitter coupled to the second node and its base coupled to a third node;
• a third transistor having its base and collector coupled to the third node;
• a fourth transistor having its collector and base being coupled to a fourth node, and its emitter coupled to the first voltage supply rail Vcc at the first node;
• a second voltage supply rail Vee coupled to a fifth node;
• a second pre-driver sub-stage circuit coupled to the sixth node, the second pre-driver sub-stage circuit further comprising:
• a fifth transistor having its emitter coupled to the second voltage supply rail Vee at the fifth node, and its base coupled to the sixth node;
• a sixth transistor having its emitter coupled to the sixth node, its base coupled to a seventh node, and its collector coupled to the second node;
• a seventh transistor having its base and collector coupled to a seventh node;
• and its emitter coupled to an eighth node;
• an eighth transistor having its collector and base being coupled to the eighth node, and its emitter coupled to the second voltage supply rail Vee at the fifth node;
• a cross connection between the second transistor's collector and the sixth transistor's emitter at the sixth node, and the second transistor's emitter and the sixth transistor's collector at the second node, the cross connection resulting in a proportion of any error current flowing into the second transistor's emitter and sixth transistor's emitter to flow out through the second transistor's collector and the sixth transistor's collector into the base of the first transistor and the base of the fifth transistor;
• a first current source coupled between the first voltage supply rail Vcc at the first node and the second node;
• a second current source coupled between the first voltage supply rail Vcc at the first node and the seventh node;
• a third current source coupled between the second voltage supply rail Vee at the fifth node and at the third node;
• a fourth current source coupled between the second voltage supply rail Vee at the fifth node and the sixth node;
• a final sub-stage, comprising:
• a first final sub-stage circuit further conditioning the positive portion of the current signal provided by the first pre-driver sub-stage circuit, the first final sub-stage circuit comprising:
• a ninth transistor having its emitter coupled to the first transistor's collector at a ninth node, and its base coupled to a tenth node and its collector coupled to the second voltage supply rail Vee at the fifth node;
• a tenth transistor having its base coupled to the ninth node, and its collector coupled to the first voltage supply Vcc rail at the first node;
• a second final sub-stage circuit further conditioning the negative portion of the current signal, provided by the second pre-driver sub-stage circuit, the second final sub-stage circuit comprising:
• an eleventh transistor having its emitter coupled to the fifth transistor's collector at an eleventh node, its base coupled to the ninth transistor's base and collector at the tenth node and its collector coupled to the first voltage supply rail Vcc at the first node;
• a twelfth transistor having its base coupled to the eleventh node, and its collector coupled to the second voltage supply rail Vee at the fifth node;
• a twelfth node interconnecting the tenth transistor's emitter with the twelfth transistor's emitter;
• and
• an output terminal coupled to the twelfth node.

A method of amplifying a signal, comprising the steps of:

• biasing a plurality of transistors in a pre-driver sub-stage;
• biasing a plurality of transistors in a final sub-stage;
• routing the positive cycle of the signal through a first, biased pre-driver sub-stage circuit;
• routing the negative cycle of the signal through a second, biased pre-driver sub-stage circuit;
• amplifying the positive cycle of the signal in the first, biased pre-driver sub-stage circuit;
• amplifying the negative cycle of the signal in the second, biased pre-driver sub-stage circuit;
• routing the amplified positive cycle of the signal to a first, biased final sub-stage circuit;
• routing the amplified negative cycle of the signal to a second, biased final sub-stage circuit;
• further amplifying the positive cycle of the signal in a first, biased final sub-stage circuit in tandem with the pre-driver sub-stage amplification action;
• further amplifying the negative cycle of the signal in a second, final sub-stage circuit in tandem with the pre-driver sub-stage amplification action;
• employing a plurality of translinear loops in the pre-driver sub-stage circuits and final sub-stage circuits so as to preserve the amplitude, frequency and phase characteristics of the signals during routing and amplification;
• and
• joining in phase the amplified portions of the positive and negative signal at an output stage terminal in a manner that results in high linearity and low distortion of an output signal when compared to the input signal

A method of amplifying signals in an operational amplifier output stage, comprising the steps of:

• generating bias currents in a pre-driver sub-stage and a final sub-stage;
• inputting the signals into the pre-driver sub-stage and a final sub-stage;
• amplifying the signals in tandem in the pre-driver sub-stage and final sub-stage;
• employing a plurality of translinear loops in the pre-driver sub-stage and final sub-stage such that there is minimal signal loss in the pre-driver sub-stage and the final sub-stage;
• and
• using localized feedback principles so as to achieve high linearity and low distortion of an output signal when compared to the input signal.