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US 2003/0097392 A1Published application
Four-rail NCL incrementor/decrementor
OwnerSteven R. Mastellerinventor
Life of this patent
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Abstract
A four-rail incrementor/decrementor circuit is presented. The circuit is capable of operating in an asynchronous (i.e., lacking a clock signal) environment. The basic circuit can be cascaded to build incrementor/decrementors that can handle numbers of arbitrarily large size. The circuit can also achieve a 50% power savings over two-rail versions.
Claims34
An incrementor/decrementor comprising:
- m control paths defining a MEAG, where m is a positive integer;
- n input paths defining a MEAG, where n is a positive integer greater than two;
- circuitry configured to judge every different combination of each one of said m control paths with each one of said n input paths;
- and
- n output paths defining a MEAG configured to pass input data received on said input paths operated on as per control data received at said control paths.
2 more elements
A multi-stage incrementor/decrementor comprising:
- at least one incrementor/decrementor cell aligned along at least one control data path, each of said at least one incrementor/decrementor cell comprising:
- (a) m control paths defining a MEAG, where m is a positive integer;
- (b) n input paths defining a MEAG, where n is a positive integer greater than two;
- (c) circuitry configured to judge every combination of each one of said m control paths with each one of said n input paths;
- (d) n output paths defining a MEAG configured to pass input data received on said input paths operated on as per control data received at said control paths
- (e) m control next paths defining a MEAG configured to pass wrap-around information,
- said control next paths of an upstream one of said at least one incrementor/decrementor cells being connected to said control paths of an adjacent downstream incrementor/decrementor cell.
4 more elements
A multi-stage incrementor/decrementor comprising:
- a first cell capable of calculating a least significant MEAG comprising:
- (a) m−1 control paths defining a MEAG, where m is a positive integer greater than one;
- (b) n input paths defining a MEAG, where n is a positive integer greater than two;
- (c) first circuitry configured to judge every combination of each one of said m−1 control paths with each one of said n input paths;
- (d) n output paths defining a MEAG configured to pass input data received on said input paths operated on as per control data received at said control paths;
- (e) m control next paths defining a MEAG configured to pass wrap-around information;
- at least one next cell capable of calculating an intermediary MEAG comprising;
- (f) m control paths defining a MEAG
- (g) n input paths defining a MEAG;
- (h) second circuitry configured to judge every combination of each one of said m control paths with each one of said n input paths;
- (i) n output paths defining a MEAG configured to pass input data received on said input paths operated on as per control data received at said control paths;
- (j) m control next paths defining a MEAG configured to pass wrap-around information;
- a last cell capable of calculating a most significant MEAG comprising:
- (k) m control paths defining a MEAG;
- (l) n input paths defining a MEAG;
- (m) third circuitry configured to judge every combination of each one of said m control paths with each one of said n input paths;
- (n) n output paths defining a MEAG configured to pass input data received on said input paths operated on as per control data received at said control paths;
- said first, at least one next, and last cells aligned along at least one control path, wherein:
- each of said first and said at least one next cell is capable of forwarding borrow and carry signals to the adjacent downstream cell, and each of said at least one next and last cell is capable of receiving borrow and carry signals from the adjacent upstream cell.
16 more elements
A multi-stage incrementor/decrementor comprising:
- a first cell capable of calculating a least significant MEAG comprising:
- (a) M−1 control paths defining a MEAG, where m is a positive integer greater than one;
- (b) n input paths defining a MEAG, where n is a positive integer greater than two;
- (c) first circuitry configured to judge every combination of each one of said m−1 control paths with each one of said n input paths;
- (d) n output paths defining a MEAG configured to pass input data received on said input paths operated on as per control data received at said control paths;
- (e) m control next paths defining a MEAG configured to pass wrap-around information;
- a last cell capable of calculating a most significant MEAG comprising:
- (f) m control paths defining a MEAG;
- (g) n input paths defining a MEAG;
- (h) second circuitry configured to judge every combination of each one of said m control paths with each one of said n input paths;
- (i) n output paths defining a MEAG configured to pass input data received on said input paths operated on as per control data received at said control paths;
- said first and last cells aligned along at least one control path, wherein:
- said first cell is capable of forwarding borrow and carry signals downstream to said last cell.
10 more elements
Dependencies are inferred from the claim text.