US 2003/0084362 A1 · Method and apparatus for generating and synchronizing multiple clocks

Abstract

Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Claims17

Dependent claims

A system for synchronizing a plurality of data channels, the system comprising:

a core circuit having a clock distribution circuit, the core circuit providing a plurality of data streams at a frequency of a core clock signal carried by the clock distribution circuit;
a first phase-locked loop circuit generating a plurality of clock signals, wherein a first clock signal from the plurality of clock signals has the same frequency and substantially the same phase as the core clock signal carried by the clock distribution circuit;
and
a plurality of channel circuits coupled to the core circuit and to the first phase-locked loop circuit, the channel circuits converting the plurality of data streams, received at a frequency of the first clock signal, into a plurality of serial data streams at a frequency of a second clock signal from the plurality of clock signals.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for generating and synchronizing multiple clocks

Life of this patent

Method and apparatus for generating and synchronizing multiple clocks

Life of this patent

Abstract

Claims17