Semiconductor device

Abstract

In the output circuit, at a subsequent stage of a gate circuit operating with a power supply voltage related to a first power supply voltage, a latch circuit formed of an inverter circuit and a MOS transistor is arranged, and is supplied with a second power supply voltage as an operating power supply voltage. An output buffer circuit is driven in accordance with an output signal of the latch circuit. When the first power supply voltage is powered down, the latch circuit receiving and operating with the second power supply voltage holds a signal voltage to be attained in a standby state and thus the output buffer circuit is reliably held in an output high impedance state. In a semiconductor device of a double power supply configuration, even when one power supply is powered down, the output buffer circuit can reliably be set to an output high impedance state.

Dependencies are inferred from the claim text.