Semiconductor wafer, method of manufacturing semiconductor wafer having bumps, semiconductor chip having bumps and method of manufacturing the same, semiconductor device, circuit board, and electronic equipment
AssigneeSeiko Epson Corporation
InventorHiroshi Ohara
Life of this patent
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Abstract
A semiconductor wafer includes a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips; a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips; and a conductor formed in a layer lower than the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads.
Claims28
A semiconductor wafer comprising:
- a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
- a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips;
- and
- a conductor formed in a layer lower than the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads.
A semiconductor wafer comprising:
- a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
- a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips;
- and
- a conductive film formed on the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads,
- wherein the conductive film is formed so that the at least two of the pads are electrically isolated when a portion of the conductive film in the second region is removed.
A method of manufacturing a semiconductor wafer having bumps comprising:
- forming the bumps by electroless plating on respective pads of a semiconductor wafer having a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips,
- wherein the plurality of pads is formed in a plurality of first regions to be the plurality of semiconductor chips, and
- wherein the electroless plating is performed in a state in which at least two of the pads are electrically connected by a conductor formed in a layer lower than the pads through a second region, which is located between two of the first regions.
A method of manufacturing a semiconductor wafer having bumps comprising:
- forming a conductive film on a plurality of pads of a semiconductor wafer having a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips so as to electrically connect at least two of the pads;
- and
- forming bumps on the conductive film in a region over each of the pads by electroless plating.
A method of manufacturing a semiconductor chip having bumps comprising cutting a semiconductor wafer,
- wherein the semiconductor wafer includes:
- a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
- a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips;
- a conductor formed in a layer lower than the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads;
- and
- bumps formed on at least two of the electrically connected pads, respectively, and
- wherein the semiconductor wafer is cut along the second region.
A method of manufacturing a semiconductor chip having bumps comprising cutting a semiconductor wafer,
- wherein the semiconductor wafer includes:
- a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
- a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips;
- a conductive film formed on the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads;
- and
- bumps formed on the conductive film in a region over the respective pads, and
- wherein the semiconductor wafer is cut along the second region.
Dependencies are inferred from the claim text.