Semiconductor memory having storage cells storing multiple bits and a method of manufacturing the same

A transistor comprising:

• a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other;
• a first insulation layer formed on a top of the projection;
• a pair of source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection;
• second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall;
• a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers;
• third insulation layers each being formed on one of said floating gates;
• a control gate facing said pair of floating gates via third insulation layers and facing the top of the projection via said first insulation layer;
• and
• counter-conductivity type regions formed on the side walls of the projection and contacting said source/drain regions.

A transistor comprising:

• a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other;
• a first insulation layer formed on a top of the projection;
• a pair of source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection;
• second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall;
• a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers;
• third insulation layers each being formed on one of said floating gates;
• and
• a control gate facing said pair of floating gates via third insulation layers and facing the top of the projection via said first insulation layer;
• said control gate forming a first capacitance against the top of the projection via said first insulation layer, said floating gates forming a second capacitance against said source/drain regions via said second insulation layers, the first capacitance being higher than the second capacitance.

A transistor comprising:

• a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other;
• a first insulation layer formed on a top of the projection;
• a pair of source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection;
• second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall;
• a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers;
• third insulation layers each being formed on one of said floating gates;
• and
• a control gate facing said pair of floating gates via third insulation layers and facing the top of the projection via said first insulation layer;
• said floating gates being coupled in capacitance with a first capacitance established against the side walls and the top of the projection and said source/drain regions via said second insulation layers, and a second capacitance established against said control gate via said third insulation layers, the first capacitance being formed larger.

A semiconductor memory comprising a plurality of cell transistors arranged in a direction of row and a direction of column, each of said plurality of cell transistors comprising:

• a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other;
• a first insulation layer formed on a top of the projection;
• a pair of source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection;
• second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall;
• a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers;
• third insulation layers each being formed on one of said floating gates;
• and
• a control gate facing said pair of floating gates via third insulation layers and facing the top of the projection via said first insulation layer;
• the projection having a root portion formed to connect said source/drain regions with a straight line, the root portion being higher in concentration of the one conductivity type of impurity than a remaining portion of the projection.

A semiconductor memory comprising a plurality of cell transistors arranged in a direction of row and a direction of column, each of said plurality of cell transistors comprising:

• a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other;
• a first insulation layer formed on a top of the projection;
• a pair of source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection;
• second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall;
• a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers;
• third insulation layers each being formed on one of said floating gates;
• a control gate facing said pair of floating gates via third insulation layers and facing the top of the projection via said first insulation layer;
• and
• counter-conductivity type regions formed on the side walls of the projection and contacting said source/drain regions.

A semiconductor memory comprising a plurality of cell transistors arranged in a direction of row and a direction of column, each of said plurality of cell transistors comprising:

• a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other;
• a first insulation layer formed on a top of the projection;
• a pair of source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection;
• second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall;
• a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers;
• third insulation layers each being formed on one of said floating gates;
• and
• a control gate facing said pair of floating gates via third insulation layers and facing the top of the projection via said first insulation layer;
• said control gate forming a first capacitance against the top of the projection via said first insulation layer, said floating gates forming a second capacitance against said source/drain regions via said second insulation layers, the first capacitance being higher than the second capacitance.

A semiconductor memory comprising a plurality of cell transistors arranged in a direction of row and a direction of column, each of said plurality of cell transistors comprising:

• a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other;
• a first insulation layer formed on a top of the projection;
• a pair of source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection;
• second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall;
• a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers;
• third insulation layers each being formed on one of said floating gates;
• and
• a control gate facing said pair of floating gates via third insulation layers and facing the top of the projection via said first insulation layer;
• said floating gates being coupled in capacitance with a first capacitance established against the side walls and the top of the projection and said source/drain regions via said second insulation layers, and a second capacitance established against said control gate via said third insulation layers, the first capacitance being formed larger.

A method of manufacturing a transistor, comprising the steps of:

• (a) implanting an impurity into a primary surface of a one-conductivity type semiconductor substrate to form a first region with lower impurity concentration and a second region with higher impurity concentration in an order from the primary surface in a depth direction of the substrate;
• (b) forming trenches in the primary surface to a depth at which the trench has a bottom reaching the second region to form a projection having a pair of side walls opposite to each other;
• (c) implanting a counter-conductivity type impurity in the bottom of the trench to form a source/drain region at the bottom;
• (d) forming a first insulation layer on the source/drain region and the side walls of the trench;
• (e) forming a floating gate at least partially on the side walls of the projection and the source/drain region via the first insulation layer;
• (f) forming a second insulation layer on a top of the projection;
• (g) forming a third insulation layer on the floating gate;
• and
• (h) forming a control gate on the second and third insulation layers.

A method of manufacturing a transistor, comprising the steps of:

• (a) forming a trench in a primary surface of a one-conductivity type semiconductor substrate to form a projection having a pair of side walls opposite to each other;
• (b) implanting a counter-conductivity type impurity in a bottom of the trench through a self-alignment process with the projection used as a mask preventing the impurity from being implanted into the projection to form a source/drain region in the bottom;
• (c) forming a first insulation layer on the source/drain region and the side walls of the trench;
• (d) forming a floating gate at least partly on the side walls of the projection and the source/drain regions via the first insulation layer;
• (e) forming a second insulation layer on a top of the projection;
• (f) forming a third insulation layer on the floating gate;
• and
• (g) forming a control gate on the second and third insulation layers.