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US 2003/0080332 A1Published application
Charge carrier extracting transistor
AssigneeQinetiq Limited
InventorTimothy J Phillips
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AssigneeQinetiq Limited
InventorTimothy J Phillips
Estimating the term…
An extracting transistor (10)—an FET—includes a conducting channel extending via a p-type InSb quantum well (22) between p-type InAlSb layers (20, 24) of wider band-gap. One of the InAlSb layers (24) incorporates an ultra-thin n-type δ-doping layer (28) of Si, which provides a dominant source of charge carriers for the quantum well (22). It bears n+ source and drain electrodes (30a, 30b) and an insulated gate (30c). The other InAlSb layer (20) adjoins a barrier layer (19) of still wider band-gap upon a substrate layer (14) and substrate (16) with electrode (18). Biasing one or both of the source and drain electrodes (30a, 30b) positive relative to the substrate electrode (18) produces minority carrier extraction in the quantum well (22) reducing its intrinsic contribution to conductivity, taking it into an extrinsic saturated regime and reducing leakage current.
An extracting transistor characterised in that:
A transistor according to any preceding claim characterised in that it includes a δ-doping layer arranged to be a dominant source of charge carriers for the quantum well (22).
A transistor according to any preceding claim characterised in that it has an n+-p−-quantum well—p−-p+-p+ diode structure.
A transistor according to any preceding claim characterised in that it has an n+-p−-quantum well—p−-p+ diode structure.
A transistor according to any preceding claim characterised in that it includes a gate contact (34c) insulated from the active region (24) by insulating material (32).
A method of obtaining transistor operation characterised in that it includes the steps of:
Dependencies are inferred from the claim text.