Control gate decoder for twin MONOS memory with two bit erase capability

A method for selecting a storage site within a twin MONOS flash memory for reading and programming using bit line override selection, comprising:

• a) selecting a first memory cell containing a first and a second storage site,
• b) selecting said first storage site within said first memory cell,
• c) selecting a first control gate above said first storage site,
• d) applying a “selected” voltage to said first control gate,
• e) selecting a second control gate above an unselected storage site within a second memory cell which is immediately adjacent to either side of said first memory cell,
• f) applying an “override” voltage to a second control gate,
• g) selecting a third control gate within a third memory cell which is not immediately adjacent to said first memory cell,
• h) applying an “unselected” voltage to said third control gate.

A control gate line decoder for an array containing twin MONOS flash memory cells, comprising:

• a) a decoder for control gate lines of a memory array,
• b) said control gate lines connected to a plurality of twin MONOS memory cells within said memory array,
• c) said decoder containing a plurality of decoder units connected to a plurality of said control lines,
• d) said plurality of decoder units divided into a plurality of odd and a plurality of even assigned addresses matching address of said memory cells,
• e) said plurality of odd assigned address decoder units connecting a low voltage or an odd assigned voltage to control gate lines with odd assigned addresses,
• f) said plurality of even assigned address decoder units connecting said low voltage or an even assigned voltage to control gate lines with even assigned addresses.

A means for decoding control gate signals for a twin MONOS flash memory, comprising:

• a) a first decoding means to select a first voltage from a first plurality of voltages to connect to a first control gate line,
• b) a second decoding means to select a second voltage from a second plurality of voltages to connect to a second control gate line,
• c) a third decoding means to select a third voltage from said first plurality of voltages or from said second plurality of voltages to connect to a third control gate line,
• d) a first addressing means to assign said first plurality of voltages to even addressed control lines,
• e) a second addressing means to assign said second plurality of voltages to odd addressed control lines.