US 2003/0079192 A1Published application

Method for generating a partitioned ic layout

AssigneeSilicon Perspective Corporation

InventorsKit-Lam Cheong, Wei-Jin Dai, Hsi-Chuan Chen, Patrick John Eichenseer

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Abstract

When generating a layout for an integrated circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout. The partitions are then separately placed and routed a manner consistent with the spatial and timing constraints imposed on each partition by the floor plan and the timing budget.

Claims21

Dependent claims

A method for converting a first netlist modeling an integrated circuit (IC) as a network of interconnected cells into an output layout indicating the cells' positions within the semiconductor substrate, and describing structures for routing signals between the cells, wherein the first netlist organizes the cells into a logical hierarchy of modules, and wherein the layout is to satisfy a plurality of timing constraints, each indicating a maximum path delay for a separate signal path within the IC, the method comprising the steps of:

a. generating a trial layout placing and interconnecting all the cells of the IC in accordance with the first netlist model of the IC in a manner that is biased toward grouping cells of the same module near one another in the semiconductor substrate;
b. producing a floorplan allocating a separate portion of semiconductor substrate area to each of a plurality of partitions, each partition including a separate set of the modules, wherein the floorplan allocates a portion of substrate area to each partition with regard to an amount of substrate area modules forming that partition span in the trial layout;
c. generating a timing budget allocating a portion of each signal path's maximum allowable signal path delay to each signal path section to be included in a separate one of said partitions in proportion to an estimated path delay through that signal path section as described in the trial layout;
d. generating for each partition included in the floorplan a separate partition layout positioning and interconnecting cells included in the partition in a manner that biased toward placing each partition within the area of the semiconductor substrate the floorplan allocates to that partition, and in a manner that is biased toward limiting the signal path delay through each of said signal path sections to the portion of the maximum signal path delay the timing budget allocates to that signal path section;
and
e. generating a full-chip layout for the entire IC incorporating each partition layout generated at step d.

3 more elements

A method for converting a netlist modeling an integrated circuit (IC) as a network of interconnected cells into an output layout including descriptions of the cells, descriptions of positions of the cells within a semiconductor substrate, and descriptions of structures that route signals between the cells, wherein the netlist organizes the cells into a logical hierarchy of modules, and wherein the IC layout is subject to a set of timing constraints specifying maximum allowable signal path delays for signal paths within the IC, the method comprising the steps of:

a. processing the netlist to generate a trial layout for the entire IC, including descriptions of the cells forming the IC, descriptions of their positions within the semiconductor substrate, and descriptions of structures for routing signals between the cells;
b. developing a floorplan allocating substrate area to each of a plurality of partitions with modules being distributed among the partitions based on sizes and relative positions of substrate areas which the trial layout indicates encompass cells of the modules;
and
c. generating a timing budget for each signal path having a timing constraint, wherein when a signal path includes sections in modules distributed to more than one partition, the timing budget allocates a separate portion of the timing constraint to each of the signal path sections.

1 more element

Dependencies are inferred from the claim text.