Combinational test pattern generation method and apparatus
AssigneeNEC Electronics Corporation
InventorWern-Yan Koe
Life of this patent
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Abstract
A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.
Claims40
A method comprising:
- coupling a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced;
- and
- applying the resultant scan chain test pattern to at least one combinational logic circuit.
An apparatus comprising:
- at least one shadowed register bank;
- and
- said at least one shadowed register bank operably connected to a combinational logic circuit.
A system comprising:
- means for coupling a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced;
- and
- means for applying the resultant scan chain test pattern to at least one combinational logic circuit.
Dependencies are inferred from the claim text.