Interface between different clock rate components

A circuit for transferring a real-time data flow from a first component operable at a first clock rate to a second component operable at a second clock rate wherein said second clock rate is higher than said first clock rate, said circuit comprising:

• a first clock signal source of said first clock rate;
• a second clock signal source of said second clock rate;
• a first buffer operable at either said first clock rate or said second clock rate and coupled to said first component and said second component;
• a second buffer operable at either said first clock rate or said second clock rate and coupled to said first component and said second component;
• a clock switch coupled to said first buffer and to said second buffer and coupled to said first and second clock signal sources, said clock switch being operable to couple said first clock signal source to either said first buffer or said second buffer and operable to couple said second clock signal source to the other of said first buffer and said second buffer when one of said buffers is substantially full.

A method for interfacing between a first component operable at a first clock rate and a second component operable at a second clock rate wherein said second clock rate is higher than said first clock rate, comprising the steps of:

• transferring data from said first component to a first buffer operable at said first clock rate;
• copying data from said first buffer to a second buffer operable at said second clock rate when said first buffer is substantially full;
• and
• prompting said second component to access said data in said second buffer when said copying step is completed.