Phase locked loop with offset cancellation

A phase locked loop comprising:

• a controlled oscillator to generate a variable output frequency signal in response to a tune signal;
• a feedback frequency divider coupled to the controlled oscillator, operable to generate a divided frequency signal from the variable output frequency signal;
• a phase detector to generate an error signal representing a difference between a reference frequency signal and the divided frequency signal, the error signal including a series of pulses that correspond to the difference;
• a loop filter to filter the error signal and generate the tune signal, the loop filter including an amplifier;
• and
• an offset cancellation circuit, responsive to the error signal, to supply a compensation signal to the loop filter to compensate for an error component associated with the amplifier.

A phase locked loop comprising:

• means for generating a variable output frequency signal corresponding to a tune signal;
• means for frequency dividing the variable output frequency signal such that a divided frequency signal is generated;
• means for detecting a difference between a reference frequency signal and the divided frequency signal;
• means for generating an error signal representing the difference, the error signal including a series of pulses to represent the difference;
• means for filtering to filter the error signal and generate the tune signal;
• and
• an offset cancellation circuit coupled to the means for filtering, responsive to the error signal, to generate a compensation signal for reducing phase offsets associated with error components of the filtering means.

A method of generating a controlled frequency signal, comprising:

• generating a variable output frequency signal in response to a tune signal;
• in response to a gating signal, detecting a difference between a reference frequency signal and the variable output frequency signal;
• generating an error signal having a series of pulses to represent the difference;
• filtering the error signal such that the tune signal is generated;
• responsive to a sampling signal, storing the error signal during a time period when the error signal represents a phase offset of the phase locked loop;
• generating a compensating signal based upon the phase offset;
• and
• combining the compensating signal with the error signal to reduce the phase offset.