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US 2003/0076150 A1Published application
Integrated circuit interconnect routing using double pumped circuitry
AssigneeIntel Corporation
InventorSriram R. Vangal
Life of this patent
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Abstract
Circuit interconnect communication circuitry dual edge triggered latching circuits transmit two data signals over a common interconnect line during one clock cycle; on signal is transmitted during each phase of a system clock over the common interconnect line. The latching circuits may be flip-flop circuits. A repeater circuit may have dual edge triggered flip-flop circuits for repeating the common interconnect line signal on a second common interconnect line. A receiver, including dual edge triggered latching circuitry, decodes the combined incoming data signals into separate outgoing data signals.
Claims31
An apparatus, comprising:
- a transmitter circuit including a first flip-flop circuit to receive a first input signal, a second flip-flop circuit to receive a second input signal, and first logic circuitry coupled to the first and the second flip-flop circuits to transmit an interconnect signal on an interconnect line, the interconnect signal comprising the first input signal while a clock signal is in a first state and the second input signal while the clock signal is in a second state;
- and
- a repeater circuit coupled to the interconnect line, the repeater circuit including a third flip-flop circuit to receive the interconnect signal, a fourth flip-flop circuit to receive the interconnect signal, and second logic circuitry coupled to the third and the fourth flip-flop circuits to re-transmit the interconnect signal.
An apparatus, comprising:
- a repeater circuit coupled to a first interconnect line having a composite interconnect signal including a first data signal and a second data signal, wherein the composite interconnect signal comprises the first data signal while a clock signal is in a first state and the second data signal while the clock signal is in a second state, the repeater circuit including a first flip-flop circuit to receive the composite interconnect signal, a second flip-flop circuit to receive the composite interconnect signal, and logic circuitry coupled to the first and second flip-flop circuits to re-transmit the composite interconnect signal on a second interconnect line;
- and
- a receiver circuit coupled to the second interconnect line, wherein the receiver circuit includes a third flip-flop circuit and a fourth flip-flop circuit to receive the re-transmitted composite interconnect signal and to separate the re-transmitted composite interconnect signal into the first data signal and the second data signal in response to the clock signal.
A circuit comprising:
- a first circuit coupled to interconnect circuitry including a transmitter circuit capable of receiving multiple input signals and providing a single output signal on a first interconnect line in response to a clock signal, the single output signal comprising a first one of the multiple input signals while the clock signal is in a first state and a second one of the multiple input signals while the clock signal is in a second state, and a repeater circuit capable of receiving the single output signal on the first interconnect line and re-transmitting the single output signal on a second interconnect line;
- and
- a second internal circuit coupled to the second interconnect line.
A circuit comprising:
- a first circuit coupled to interconnect circuitry including a repeater circuit coupled to a first interconnect line having a composite interconnect signal including a first data signal and a second data signal, wherein the composite interconnect signal comprises the first data signal while the clock signal is in a first state and the second data signal while the clock signal is in a second state, the repeater circuit including a first flip-flop circuit to receive the composite interconnect signal, a second flip-flop circuit to receive the composite interconnect signal, and logic circuitry coupled to the first and second flip-flop circuits to re-transmit the composite interconnect signal on a second interconnect line, and a receiver circuit coupled to the second interconnect line, wherein the receiver circuit includes a third flip-flop circuit and a fourth flip-flop circuit to receive the re-transmitted composite interconnect signal and to separate the re-transmitted composite interconnect signal into the first data signal and the second data signal in response to the clock signal;
- and
- a second circuit coupled to the receiver circuit.
A method of reducing circuit interconnect routing, the method comprising:
- latching a first data signal in response to a rising edge of a system clock;
- latching a second data signal in response to a falling edge of the system clock;
- transmitting the first data signal and the second data signal on an interconnect line as a composite signal, the first data signal being transmitted on the interconnect line when the system clock is in a high state, and the second data signal being transmitted on the interconnect line when the system clock is in a low state;
- receiving the composite signal at a repeater circuit;
- separating the composite signal into a first output data signal and a second output data signal at the repeater circuit;
- and
- re-combining the separated first and second output data signals at the repeater circuit to form a second composite signal to be transmitted to another circuit.
4 more elements
Dependencies are inferred from the claim text.