US 2003/0076149 A1 · Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device

Abstract

Disclosed is a sampling level converter circuit having a fewer number of terminals and reduced power consumption, as well as an expanding circuit having such a sampling level converter circuit. The sampling level converter circuit includes first to third MOS transistors connected serially between a higher-potential power-supply and a lower-potential power-supply; a first capacitor connected to a connection node of the first and second MOS transistors; a fourth MOS transistor connected between an input terminal and the gate terminal of the third MOS transistor; and a second capacitor connected to the gate of the third MOS transistor. A sampling pulse signal is supplied to the gates of the first and second MOS transistors, and a signal obtained by inverting this sampling pulse signal is supplied to the gate of the fourth MOS transistor.

Claims37

Dependent claims

A sampling level converter circuit comprising:

a switch element inserted in a charging path of an output node;
a switch element inserted in a discharging path of the output node;
means for turning on the switch element inserted in the charging path of the output node, in a setup time-interval, on the basis of a sampling control signal supplied thereto, thereby precharging the output node to a voltage of the higher-potential power-supply;
and
means for sampling an input signal voltage;
wherein the discharging path of the output node is held in an off state based upon the sampling control signal in the setup time-interval;
the switch element inserted in the discharging path of the output node is turned on and off in accordance with a logic value of the input signal voltage sampled in the setup time-interval, in an output time-interval specified by the sampling control signal;
when the switch element inserted in the discharging path is turned on, the discharging path is set in an on state, thereby discharging the precharged output node;
and
when the switch element inserted in the discharging path is turned off, no discharging of the precharged output node takes place.

7 more elements

A sampling level converter circuit comprising:

first to third switch elements connected serially between a higher-potential power-supply and a lower-potential power-supply;
a first capacitor connected to a connection node of said first and second switch elements;
a fourth switch element connected between an input terminal, to which an input signal is supplied, and a control terminal of said third switch element;
and
a second capacitor connected to a connection node of the control terminal of said third switch element and said fourth switch element;
wherein a first sampling control signal is supplied in common to both a control terminal of said first switch element and a control terminal of said second switch element, whereby one of said first and second switch elements is turned off when the other is turned on;
a second sampling control signal is supplied to a control terminal of said fourth switch;
and
an output signal is derived directly or indirectly from a terminal voltage of said first capacitor.

6 more elements

A 2-phase expanding circuit comprising:

a first sampling level converter circuit including:
first to third switch elements connected serially between a higher-potential power-supply and a lower-potential power-supply;
a first capacitor connected to a connection node of said first and second switch elements;
a fourth switch element connected between an input terminal, to which an input signal is supplied, and a control terminal of said third switch element;
and
a second capacitor connected to a connection node of the control terminal of said third switch element and said fourth switch element;
wherein a first sampling control signal is supplied in common to both a control terminal of said first switch element and a control terminal of said second switch element;
and
a second sampling control signal, which is the complement to the first sampling control signal, is supplied to a control terminal of said fourth switch;
a first group of inverters of an even number of stages connected in cascade, an initial stage of the inverters receiving terminal voltage of said first capacitor supplied thereto;
a first master/slave latch for storing an output signal of a final stage of said first group of inverters when the first sampling control signal is a first logic value, and for outputting the stored signal when the second sampling control signal is the first logic value;
a first latch for receiving the output signal from said first master/slave latch, and for outputting the signal received as an odd-numbered signal when the first sampling control signal is the first logic value;
a second sampling level converter circuit including:
fifth to seventh switch elements connected serially between the higher-potential power-supply and the lower-potential power-supply;
a third capacitor connected to a connection node of said fifth and seventh switch elements;
an eighth switch element connected between the input terminal, to which the input signal is supplied, and a control terminal of said seventh switch element;
and
a fourth capacitor connected to a connection node of the control terminal of said seventh switch element and said eighth switch element;
wherein the second sampling control signal is supplied in common to both a control terminal of said fifth switch element and a control terminal of said sixth switch element;
and
the first sampling control signal is supplied to a control terminal of said eighth switch;
a second group of inverters of an even number of stages connected in cascade, an initial stage of the inverters receiving terminal voltage of said third capacitor supplied thereto;
and
a second master/slave latch for storing an output signal of a final stage of said second group of inverters when the second sampling control signal is the first logic value, and for outputting the stored signal as an even-numbered signal when the first sampling control signal is the first logic value;
the odd-numbered signal and the even-numbered signal being output in parallel in sync with transition of the first sampling control signal to the first logic value.

22 more elements

A multi-phase expanding circuit comprising:

a first sampling level converter circuit including:
first to third switch elements connected serially between a higher-potential power-supply and a lower-potential power-supply;
a first capacitor connected to a connection node of said first and second switch elements;
a fourth switch element connected between an input terminal, to which an input signal is supplied, and a control terminal of said third switch element;
and
a second capacitor connected to a connection node of the control terminal of said third switch element and said fourth switch element;
wherein a first sampling control signal is supplied in common to both a control terminal of said first switch element and a control terminal of said second switch element;
and
a second sampling control signal, which is the complement to the first sampling control signal, is supplied to a control terminal of said fourth switch;
a first group of inverters of an even number of stages connected in cascade, an initial stage of the inverters receiving terminal voltage of said first capacitor supplied thereto;
a first master/slave latch for storing an output signal of a final stage of said first group of inverters when the first sampling control signal is a first logic value, and for outputting the stored signal when the second sampling control signal is the first logic value;
a first latch for receiving the output signal from said first master/slave latch, and for outputting the signal received as an odd-numbered signal when the first sampling control signal is the first logic value;
a second sampling level converter circuit including:
fifth to seventh switch elements connected serially between the higher-potential power-supply and the lower-potential power-supply;
a third capacitor connected to a connection node of said fifth and seventh switch elements;
an eighth switch element connected between the input terminal, to which the input signal is supplied, and a control terminal of said seventh switch element;
and
a fourth capacitor connected to a connection node of the control terminal of said seventh switch element and said eighth switch element;
wherein the second sampling control signal is supplied in common to both a control terminal of said fifth switch element and a control terminal of said sixth switch element;
and
the first sampling control signal is supplied to a control terminal of said eighth switch;
a second group of inverters of an even number of stages connected in cascade, an initial stage of the inverters receiving terminal voltage of said third capacitor supplied thereto;
a second master/slave latch for storing an output signal of a final stage of said second group of inverters when the second sampling control signal is the first logic value, and for outputting the stored signal as an even-numbered signal when the first sampling control signal is the first logic value;
wherein the odd-numbered signal and the even-numbered signal are output in parallel in sync with transition of the first sampling control signal to the first logic value;
a first group of master/slave latches of M-number of stages connected in cascade, for storing an input signal applied thereto when the second sampling control signal is the first logic value, and for outputting the stored signal when the first sampling control signal is the first logic value;
the odd-numbered signal being supplied to a first stage of said first group of master/slave latches;
a first group of latches of (M+1)-number, arranged in parallel for latching the odd-numbered signal and respective ones of outputs from said first group of master/slave latches in response to a third signal obtained by frequency-dividing the frequency of the input signal by 2(M+1);
a second group of master/slave latches of M-number of stages connected in cascade, for storing an input signal applied thereto when the second sampling control signal is the first logic value, and for outputting the stored signal when the first sampling control signal is the first logic value;
the even-numbered signal being supplied to a first stage of said second group of master/slave latches;
and
a second group of latches of (M+1)-number, arranged in parallel for latching the even-numbered signal and respective ones of outputs from said second group of master/slave latches in response to the third signal;
whereby signals that have been expanded into 2(M+1)-number of phases are output in parallel from said first and second groups of latches at cycles obtained by frequency-dividing the frequency of the input signal by 2(M+1).

29 more elements

Dependencies are inferred from the claim text.

Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device

Life of this patent

Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device

Life of this patent

Abstract

Claims37