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US 2003/0075796 A1Published application
Semiconductor device
AssigneeRenesas Technology Corp.
InventorsToshiyuki Hata, Ichio Shimizu
Life of this patent
Estimating the term…
Abstract
A chip including a power MOS circuit in the high level side and a chip including a power MOS circuit in the low level side are accommodated within one sealing body. In this structure, the leads connecting the drain electrodes of the power MOS circuits in the high level and low level sides are set wide and are projected asymmetrically from both longer sides surfaces of the sealing body. Accordingly, the semiconductor device including a composite power MOSFET can be mounted easily.
Claims37
A semiconductor device comprising:
- a first semiconductor chip including a first field effect transistor;
- a second semiconductor chip including a second field effect transistor;
- a sealing body for sealing said first and second semiconductor chips;
- a first lead connected to the rear surface electrode of said first semiconductor chip and projected from a first surface of said sealing body;
- and
- a second lead connected to the rear surface electrode of said second semiconductor chip and projected from a second surface provided opposed to said first surface in said sealing body,
- wherein said first and second leads are formed wider than the other leads projected from the first and second surfaces of said sealing body in the asymmetrical relationship with each other.
4 more elements
A semiconductor device comprising:
- a first semiconductor chip including a first field effect transistor;
- an external terminal for first gate electrode and an external terminal for first source electrode formed on the first surface of said first semiconductor chip;
- a first drain electrode formed on the second surface in the opposite side of said first surface of said first semiconductor chip;
- a first pattern to which said first semiconductor chip is mounted in connection with said first drain electrode;
- a pattern for first gate disposed adjacent to said first pattern but separately from said first pattern and electrically connected to said external terminal for the first gate electrode via a bonding wire;
- a pattern for first source disposed adjacent to said first pattern but separately from said first pattern and electrically connected to said external terminal for first source electrode via a bonding wire;
- a second semiconductor chip which is different from said first semiconductor chip and includes a second field effect transistor;
- an external terminal for second gate electrode and an external terminal for second source electrode formed on the first surface of said second semiconductor chip;
- a second drain electrode formed on the second surface in the opposite side of the first surface of said second semiconductor chip;
- a second pattern to which said second semiconductor chip is mounted in connection with said second drain electrode;
- a pattern for second gate disposed adjacent to said second pattern but separately from said second pattern and is electrically connected to said external terminal for second gate electrode via a bonding wire;
- a pattern for second source disposed adjacent to said second pattern but separately from said second pattern and electrically connected to said external terminal for second source electrode via a bonding wire;
- a sealing body for sealing said first and second semiconductor chips, said first and second patterns, said patterns for first and second gates, said patterns for first and second sources and bonding wires;
- a lead for first drain integrally formed to said first pattern and projected from said first surface of sealing body;
- a lead for first gate integrally formed to said pattern for first gate and projected from said first surface of sealing body;
- a lead for first source integrally formed to said pattern of first source and projected from the second surface in the opposite side of said first surface of sealing body;
- a lead for second drain integrally formed to said second pattern and projected from said second surface of sealing body;
- a lead for second gate integrally formed to said pattern for second gate and projected from said first surface of sealing body;
- a lead for second source integrally formed to said pattern for second source and projected from said first surface of sealing body,
- wherein said leads for first and second drains are formed wider than the leads for first and second gates and the leads for first and second sources projected from said first and second surfaces of sealing body in the asymmetrical positional relationship with each other.
17 more elements
A semiconductor device comprising:
- a first semiconductor chip including a first field effect transistor;
- an external terminal for first gate electrode and an external terminal for first source electrode formed on the first surface of said first semiconductor chip;
- a first drain electrode formed on the second surface in the opposite side of said first surface of said first semiconductor chip;
- a first pattern to which said first semiconductor chip is mounted in connection with said first drain electrode of said first semiconductor chip;
- a pattern for first gate disposed near said first pattern but separately from said first pattern and electrically connected to said external terminal for first gate electrode via a bonding wire;
- a pattern for the first source disposed near said first pattern but separately from said first pattern and electrically connected to said external terminal for said first source electrode via a bonding wire;
- a second semiconductor chip which is different from said first semiconductor chip and includes a second field effect transistor;
- an external terminal for second gate electrode and an external terminal for second source electrode formed on the first surface of said second semiconductor chip;
- a second drain electrode formed on the second surface in the opposite side of said first surface of said second semiconductor chip;
- a second pattern to which said second semiconductor chip is mounted in connection with said second drain electrode of said second semiconductor chip;
- a pattern for second gate disposed near said second pattern but separately from said second pattern and is electrically connected to said external terminal of said second electrode via a bonding wire;
- a pattern for second source disposed near said second pattern but separately from said second pattern and is electrically connected to said external terminal for said second source electrode via bonding wire;
- a sealing body for sealing said first and second semiconductor chips, said first and second patterns, said patterns for first and second gates, said patterns for first and second sources, and bonding wires;
- a lead for first drain integrally formed to said first pattern and projected from said first surface of sealing body;
- a lead for first gate integrally formed to said pattern for first gate and projected from said first surface of sealing body;
- a lead for first source integrally formed to said pattern for first source and projected from said second surface in the opposite direction of said first surface of sealing body;
- a lead for second drain integrally formed to said second pattern and projected from said second surface of sealing body;
- a lead for second gate integrally formed to said pattern for second gate and projected from said first surface of sealing body;
- and
- a lead for second source integrally formed to said pattern for second source and projected from said first surface of sealing body,
- wherein said pattern for first source is electrically isolated not to be linearly connected to said second pattern.
18 more elements
A semiconductor device comprising:
- a first semiconductor chip including a first field effect transistor;
- an external terminal for first gate electrode and an external terminal for first source electrode formed on the first surface of said first semiconductor chip;
- a first drain electrode formed on the second surface in the opposite side of the first surface of said first semiconductor chip;
- a first pattern to which said first semiconductor chip is mounted in connection with said first drain electrode of said first semiconductor chip;
- a pattern for the first gate disposed near said first pattern but separately from said first pattern and electrically connected to said external terminal for said first gate via a bonding wire;
- a pattern for the first source disposed near said first pattern but separately from said first pattern and electrically connected to said external terminal of said first source via a bonding wire;
- a second semiconductor chip which is different from said first semiconductor chip and includes a second field effect transistor;
- an external terminal for the second gate electrode and an external terminal for the second source electrode formed on the first surface of said second semiconductor chip;
- a second drain electrode formed on the second surface in the opposite side of the first surface of said second semiconductor chip;
- a second pattern to which said second semiconductor chip is mounted in connection with second drain electrode of said second semiconductor chip;
- a pattern for second gate disposed near said second pattern but separately from said second pattern and is electrically connected to said external terminal of said second gate electrode via a bonding wire;
- a pattern for second source disposed near said second pattern but separately from said second pattern and electrically connected to said external terminal of said second source electrode via a bonding wire;
- a sealing body for sealing said first and second semiconductor chips, said first and second patterns, said patterns for first and second gates, said patterns for first and second sources, and bonding wires;
- a lead for the first drain integrally formed to said first pattern and projected from the first surface of said sealing body;
- a lead for the first gate integrally formed to said pattern for the first gate and projected from the first surface of said sealing body;
- a lead for the first source integrally formed to said pattern for first source and is projected from the second surface in the opposite side of the first surface of said sealing body;
- a lead for the second drain integrally formed to said second pattern and projected from the second surface of said sealing body;
- a lead for the second gate integrally formed to said pattern for the second gate and projected from the first surface of said sealing body;
- and
- a lead for the second source integrally formed to said pattern for the second source and projected from the first surface of said sealing body,
- wherein projected areas are provided to the sides opposing to each other of said first and second patterns, and said first and second patterns are disposed so that these projected areas overlap with each other in the extending direction of the opposing sides.
18 more elements
Dependencies are inferred from the claim text.