Semiconductor integrated circuit, MOS transistor, semicoductor device, robot and management system of lottery
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsShigenobu Maeda, Koichiro Mashiko
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Abstract
As a first semiconductor element and a second semiconductor element, provided are two p-type MOS transistors (11a, 11b) for forming an element pair (11). These MOS transistors (11a, 11b) are compared with each other in electronic characteristic and a result of which is utilized for determining binary logic for the element pair (11). These MOS transistors (11a, 11b) are integrated and hence, they are equally subjected to ambient temperature. As a result, the result of comparison therebetween in electronic characteristic is unlikely to be subjected to ambient temperature.
Claims18
A semiconductor integrated circuit, comprising:
- a plurality of element pairs each including a first semiconductor element and a second semiconductor element,
- wherein said first semiconductor element and said second semiconductor element are compared in electronic characteristic, a result of which being utilized for determining a binary logic for each of said plurality of element pairs.
A MOS transistor, comprising:
- a gate electrode having a planarized main surface;
- a gate insulating film;
- and
- a polycrystalline semiconductor layer including a channel region, a source region and a drain region, said polycrystalline semiconductor layer being opposed to said gate electrode through said gate insulating film with an area smaller than that of said main surface.
A MOS transistor, comprising:
- a source region;
- a drain region;
- and
- a channel region including polycrystalline semiconductor,
- wherein at least one of a channel width and a channel length of said channel region has a value that is not less than the same as and not more than 10 times an average value of a diameter of a crystal grain in said polycrystalline semiconductor.
Dependencies are inferred from the claim text.