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AssigneeKoninklijke Philip Electronics N.V.
InventorsAnton Petrus Maria Van Arendonk, Edwin Roks, Adrianus Johannes Mierop
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The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode. The invention also relates to an integrated circuit (404) obtained by means of the manufacturing method, a wafer (401) comprising an integrated circuit (404) obtained by means of the manufacturing method, and a system comprising an integrated circuit (404) obtained by means of the manufacturing method.
A method of manufacturing an integrated circuit (404) on a die (402) that is formed as a detachable part of a wafer (401) comprising a plurality of dies (402) that are separated from each other by dicing lanes (403), which method comprises a step of providing a metallization pattern (407) in at least one of the dicing lanes (403) so as to form a communication bus comprising at least one communication bus circuit (405) that forms part of the integrated circuit (404), which step is followed by a step wherein the integrated circuit (404) is tested in accordance with a predetermined testing method that utilizes the communication bus circuit (405) for communication with the integrated circuit (404), after which a step is carried out wherein the die (402) is detached from the wafer (401), characterized in that the communication bus circuit (405) is embodied so as to be able to communicate in a wafer test mode as well as in a functional mode, and said communication bus circuit communicates in the wafer test mode during the testing of the integrated circuit (404).
An integrated circuit (404) provided with a communication bus circuit (405) and situated on a die (401), which die was a detachable part of a wafer (401) during the manufacture of the integrated circuit (404), and the wafer (401) comprised a number of dies (402) that were separated from each other by means of dicing lanes (403), and a metallization pattern (407) for forming a communication bus comprising the communication bus circuit (405) was formed in at least one of the dicing lanes (403), characterized in that the communication bus circuit (405) is designed to communicate in a wafer test mode during (at least part of) the manufacture and to communicate in a functional mode during normal operation.
A wafer (401) comprising dies (402), an integrated circuit (404) being realized on at least one die, and further comprising at least one dicing lane (403) that is provided with a metallization pattern (407), characterized in that the metallization pattern (407) is designed to form a communication bus comprising at least one communication bus circuit (405) that forms part of the integrated circuit (404) and that is designed so as to be able to communicate in a wafer test mode as well as in a functional test mode.
Dependencies are inferred from the claim text.