Compiler-directed speculative approach to resolve performance-degrading long latency events in an application
AssigneeIntel Corporation
InventorsDz-Ching Ju, Youfeng Wu
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Abstract
A compiler-directed speculative approach to resolve performance-degrading long latency events in an application is described. One or more performance-degrading instructions are identified from multiple instructions to be executed in a program. A set of instructions prefetching the performance-degrading instruction is defined within the program. Finally, at least one speculative bit of each instruction of the identified set of instructions is marked to indicate a predetermined execution of the instruction.
Claims28
A method comprising:
- identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;
- defining a set of instructions within said program to prefetch said at least one performance-degrading instruction;
- and
- marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction.
A system comprising:
- means for identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;
- means for defining a set of instructions within said program to prefetch said at least one performance-degrading instruction;
- and
- means for marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction.
A computer readable medium containing executable instructions, which, when executed in a processing system, cause said processing system to perform a method comprising:
- identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;
- defining a set of instructions within said program to prefetch said at least one performance-degrading instruction;
- and
- marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction.
A system comprising:
- a memory to store a plurality of instructions to be executed in a program;
- and
- a processor coupled to said memory to identify at least one performance-degrading instruction from said plurality of instructions, to define a set of instructions within said program to prefetch said at least one performance-degrading instruction, and to mark at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction.
Dependencies are inferred from the claim text.