Instruction pair detection and pseudo ports for cache array

Abstract

Embodiments are provided in which a first and second instructions are executed in parallel. A first and a second address are generated according to the first and second instructions, respectively. The first address is used to select a data cache line of a data cache RAM and a first data bank from the data cache line. The second address is used to select a second data bank from the data cache. The first and second data banks are outputted in parallel from the data cache RAM. An instruction pair testing circuit tests the probability of the first and second instructions accessing a same data cache line of the data cache RAM. If it is unlikely that the two instructions will access a same data cache line, the second instruction is refetched and re-executed, and the second data bank is not used.

Dependencies are inferred from the claim text.