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US 2003/0074385 A1Published application
Providing a fast adder for processor based devices
AssigneeIntel Corporation
InventorJianwei Liu
Life of this patent
Estimating the term…
Abstract
In one embodiment of the present invention, a high-speed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance. The present invention may be incorporated into single or multi-bit adders.
Claims29
An adder circuit for adding a first binary number and a second binary number, the adder comprising:
- a carry evaluating circuit generating a carry production control signal representing a sum of a block of corresponding bits of the first binary number and the second binary number and an input carry value to the block, the carry production control signal comprising two signals A and B that can each have a value of either P or Q;
- and
- a conversion circuit coupled to receive the A and B outputs and the conversion circuit outputting two signals X and Y, each having a value of either P or Q, and X and Y having one of three possible values.
A microprocessor comprising:
- an arithmetic logic circuit including an adder having a carry evaluating circuit generating a carry production control signal representing a sum of a block of corresponding bits of the first binary number and the second binary number and an input carry value to the block, the carry production control signal comprising two signals A and B that can each have a value of either P or Q;
- and
- a conversion circuit coupled to receive the A and B outputs and the conversion circuit outputting two signals X and Y, each having a value of either P or Q, and X and Y having one of three possible values.
A method for adding a first and a second binary number, each having a plurality of bits, comprising:
- generating a carry production control signal representing a sum of a plurality of corresponding bits of the first binary number and the second binary number and an input carry value to the plurality of bits where the carry production control signal comprises two signals A and B that can each have a value of either P or Q;
- and
- converting the A and B signals into two signals, X and Y, representing one of three possible values.
Dependencies are inferred from the claim text.